參數(shù)資料
型號(hào): KSZ8893FQL-FX
廠商: Micrel Inc
文件頁數(shù): 102/117頁
文件大小: 0K
描述: IC SWITCH ETH 3PORT 128-PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-3273
Micrel, Inc.
KSZ8893FQL
October 2007
85
M9999-101607-1.3
Register 76 (0x4C): Remote Command 3
Bit
Name
R/W
Description
Default
7
AMM47
R/W
0
6
AMM46
R/W
0
5
AMM45
R/W
0
4
AMM44
R/W
0
3
AMM43
R/W
0
2
AMM42
R/W
0
1
AMM41
R/W
0
AMM40
R/W
If Center MC sends the “Remote Command” in register 0x42h,
this register value will be used for M47-M40 of the
Maintenance frame, instead of register 0x57h.
[AMM47:AMM40] = bits[7:0] of the KSZ8893FQL data byte if
the Operating Mode in register 0x4Ah bits[1:0] is set to “10”
0
Register 77 (0x4D): Valid MC Packet Transmitted Counter
Bit
Name
R/W
Description
Default
7
VMTX7
RO
0
6
VMTX6
RO
0
5
VMTX5
RO
0
4
VMTX4
RO
0
3
VMTX3
RO
0
2
VMTX2
RO
0
1
VMTX1
RO
0
VMTX0
RO
At both the Center and Terminal sides, this counter is
incremented when a valid maintenance packet is transmitted.
0000_0000 : No valid maintenance packet transmitted
0000_0001 : 1 valid maintenance packet transmitted
:
1111_1111 : 255 valid maintenance packets transmitted
This counter is cleared when 0x00h is written to reg. 0x44h.
0
Register 78 (0x4E): Valid MC Packet Received Counter
Bit
Name
R/W
Description
Default
7
VMRX7
RO
0
6
VMRX6
RO
0
5
VMRX5
RO
0
4
VMRX4
RO
0
3
VMRX3
RO
0
2
VMRX2
RO
0
1
VMRX1
RO
0
VMRX0
RO
At both the Center and Terminal sides, this counter is
incremented when a valid maintenance packet (good CRC,
valid OP code, valid direction) is received.
0000_0000 : No valid maintenance packet received
0000_0001 : 1 valid maintenance packet received
:
1111_1111 : 255 valid maintenance packets received
This counter is cleared when 0x00h is written to reg. 0x44h.
0
Register 79 (0x4F): Shadow of 0x58h Register
Bit
Name
R/W
Description
Default
7-0
SHA7-0
RO
For Terminal MC mode, this register is always a shadow of
register 0x58h when the OPT link is up.
For Center MC mode, this register is a shadow of register
0x58h on the initial power on reset when the OPT link is up.
After power up, if a warm reset or chip power down is
asserted, this register will retain the value of register 0x58 prior
to either of the aforementioned conditions. This is so that the
link partner’s OAM status prior to warm reset or chip power
down can be reported when the OPT link is initially re-
established. Thereafter, this register is a shadow of register
0x58h when the OPT link is up.
0x07
(Terminal side)
--------------------
0x47
(Center side)
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