參數(shù)資料
型號: KSZ8893FQL-FX
廠商: Micrel Inc
文件頁數(shù): 98/117頁
文件大?。?/td> 0K
描述: IC SWITCH ETH 3PORT 128-PQFP
標準包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-3273
Micrel, Inc.
KSZ8893FQL
October 2007
81
M9999-101607-1.3
Bit
Name
R/W
Description
Default
2
Enhanced
ML_EN
R/W
1 = Defined as follows:
In Terminal side MC mode, if a link down is detected on the
fiber or the Center side UTP, the Terminal side will disable the
TX on its UTP and turn off the LEDs to its UTP.
In Center side MC mode, this bit has no meaning.
0 = Normal operation
ML_EN pin
value during
reset
1
P1 TX_DIS
R/W
1 = Disable (tri-state) transmit to Fiber PHY
(port 1)
0 = Normal operation
0
PHY reset
R/W
1 = Reset the PHY of both PHY ports to their default states.
This bit is self-cleared after a ‘1’ is written to it.
0 = Normal operation
Note: MC (maintenance) sub-layer registers are not reset by
this bit.
1
(Powered on
value in Center
side MC mode.
After reg.
0x40h is
programmed,
this bit will be
cleared.)
--------------------
0
(Default value
for non Center
side MC mode)
Register 68 (0x44): Loop Back Setup1
Bit
Name
R/W
Description
Default
7
T7
R/W
0
6
T6
R/W
0
5
T5
R/W
0
4
T4
R/W
0
3
T3
R/W
0
2
T2
R/W
1
T1
R/W
1
0
T0
R/W
Center and Terminal sides
0000_0000 : Clear valid transmit and valid receive counters
in registers 4Dh and 4Eh. Also for center side, clear loop back
counters in registers 46h, 47h and 48h.
Center side only
0000_0001 : Send 1 MC loop back packet
0000_0010 : Send 2 MC loop back packets
:
0000_0111 : Send 7 MC loop back packets (default)
:
0110_0100 : Send 100 MC loop back
packets
other values (0x65h to 0xFFh) : N/A
1
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