參數(shù)資料
型號(hào): KSZ8995XA-EVAL
廠商: Micrel Inc
文件頁數(shù): 44/51頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8995XA
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8995XA
主要屬性: 5 個(gè)端口,100BASE-TX/100BASE-FX/10BASE-T
次要屬性: 2xMII,SNI
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: KSZ8995XAB3-ND - IC SWITCH 5-PORT 10/100 128PQFP
KSZ8995XA4-ND - IC SWITCH 5-PORT 10/100 128PQFP
576-1042-ND - IC SWITCH 10/100 5PORT 128PQFP
576-1041-ND - IC SWITCH 10/100 5PORT 128PQFP
其它名稱: 576-1642
May 2005
49
M9999-051305
KS8995XA
Micrel, Inc.
tsr
tcs
tch
trc
Supply
Voltage
RST_N
Strap-In
Value
Strap-In /
Output Pin
Figure 19. Reset Timing
Symbol
Parameter
Min
Typ
Max
Units
t
SR
Stable Supply Voltages to Reset High
10
ms
t
CS
Configuration Set-Up Time
50
ns
t
CH
Configuration Hold Time
50
ns
t
RC
Reset to Strap-In Pin Output
50
ns
Table 11. Reset Timing Parameters
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8895XA device. For
the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit
as shown in Figure 21.
VCC
R
10k
D2
C
10F
D1
CPU/FPGA
RST_OUT_n
KS8995X
RST
D1, D2: 1N4148
Figure 20. Recommended Reset Circuit.
VCC
R
10k
C
10F
D1
KS8995X
RST
D1: 1N4148
Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA
provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage.
At worst case, the both VDD core and VDDIO voltages should come up at the same time.
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