參數(shù)資料
型號： KXPC8260ZUIHBC
廠商： Freescale Semiconductor
文件頁數(shù)： 13/41頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II 480-TBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 480-LBGA
供應(yīng)商設(shè)備封裝： 408-TBGA（37.5x37.5）
包裝： 托盤
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3
Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
NOTE
Clock configurations change only after POR is asserted.
3.1
Local Bus Mode
Table 12 describes default clock modes for the MPC8260.
Table 13 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type.
Table 12. Clock Default Modes
MODCK[1–3]
Input Clock
Frequency
CPM Multiplication
Factor
CPM
Frequency
Core Multiplication Factor Core Frequency
000
33 MHz
3
100 MHz
4
133 MHz
001
33 MHz
3
100 MHz
5
166 MHz
010
33 MHz
4
133 MHz
4
133 MHz
011
33 MHz
4
133 MHz
5
166 MHz
100
66 MHz
2
133 MHz
2.5
166 MHz
101
66 MHz
2
133 MHz
3
200 MHz
110
66 MHz
2.5
166 MHz
2.5
166 MHz
111
66 MHz
2.5
166 MHz
3
200 MHz
Table 13. Clock Configuration Modes1
MODCK_H–MODCK[1–3]
Input Clock
Frequency2,3,4
CPM Multiplication
Factor2, 5
CPM
Frequency2
Core Multiplication
Factor2, 6
Core
Frequency2
0001_000
33 MHz
2
66 MHz
4
133 MHz
0001_001
33 MHz
2
66 MHz
5
166 MHz
0001_010
33 MHz
2
66 MHz
6
200 MHz
0001_011
33 MHz
2
66 MHz
7
233 MHz
0001_100
33 MHz
2
66 MHz
8
266 MHz
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