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參數(shù)資料
| 型號(hào)： | KXPC8260ZUIHBC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
12
Freescale Semiconductor
Electrical and Thermal Characteristics
2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8260 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
Table 7 lists CPM output characteristics.
Table 8 lists CPM input characteristics.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
Table 6. Output Buffer Impedances1
1 These are typical values at 65° C. The impedance
may vary by ±25% with process and temperature.
Output Buffers
Typical Impedance (
Ω)
60x bus
40
Local bus
40
Memory controller
40
Parallel I/O
46
Note:
Table 7. AC Characteristics for CPM Outputs1
1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
Spec Number
Characteristic
Max Delay (ns)
Min Delay (ns)
Max
Min
66 MHz
sp36a
sp37a
FCC outputs—internal clock (NMSI)
6
1
sp36b
sp37b
FCC outputs—external clock (NMSI)
14
2
sp40
sp41
TDM outputs/SI
25
5
sp38a
sp39a
SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
19
1
sp38b
sp39b
Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
19
2
sp42
sp43
PIO/TIMER/IDMA outputs
14
1
Note:
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