參數(shù)資料
型號(hào)： L6566BTR
廠商： 意法半導(dǎo)體
英文描述： Multi-mode controller for SMPS
中文描述： 多模式開(kāi)關(guān)電源控制器
文件頁(yè)數(shù)： 35/51頁(yè)
文件大?。?/td> 401K
代理商： L6566BTR
L6566B
Application information
35/51
5.11
OVP block
The OVP function of the L6566B monitors the voltage on the ZCD pin (11) in MOSFET’s
OFF-time, during which the voltage generated by the auxiliary winding tracks converter’s
output voltage. If the voltage on the pin exceeds an internal 5V reference, a comparator is
triggered, an overvoltage condition is assumed and the device is shut down. An internal
current generator is activated that sources 1mA out of the VFF pin (15). If the VFF voltage is
allowed to reach 2 Vbe over 5V, the L6566B will be latched off. See
Section 5.9: Latched
disable function on page 32
for more details on IC’s behavior under these conditions. If the
impedance externally connected to pin 15 is so low that the 5+2V
BE
threshold cannot be
reached or if some means is provided to prevent that, the device will be able to restart after
the Vcc has dropped below 5V. Refer to the “Application examples and Ideas” section
(
Table 8 on page 45
) for additional hints.
Figure 22. OVP Function: internal block diagram
The ZCD pin will be connected to the auxiliary winding through a resistor divider R
Z1
, R
Z2
(see
Figure 8 on page 20
). The divider ratio k
OVP
= R
Z2
/ (R
Z1
+ R
Z2
) will be chosen equal
to:
Equation 13
where Vout
OVP
is the output voltage value that is to activate the protection, Ns the turn
number of the secondary winding and Naux the turn number of the auxiliary winding.
Fault
2-bit
counter
R Q1
S
Monostable
M1
STROBE
OVP
COUT
2 μs
0.5 μs
Monostable
M2
-
+
5 V
ZCD
Counter
reset
FF
40k
5pF
PWM latch
Q
Q
S
R
11
to triggering
block
L6566B
Naux
Ns
Vout
5
k
OVP
OVP
=
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