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參數(shù)資料
| 型號： | L6611N |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER |
| 中文描述： | 數(shù)字可編程控制器二次內(nèi)務(wù)管理 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 609K |
| 代理商： | L6611N |
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L6611
20/28
3
The time intervals t1-t5 are listed below
–
t1:
UV/OC blanking of MFAULT. While Main outputs are ramping up, the UV comparators are blanked
for this interval to prevent a false turn-off. No such blanking is applied to OV faults.
–
t2:
PW-OK delay. This period starts when all monitored outputs and AC sense are above their respec-
tive UV levels and finishes at PW-OK going high.
–
t3:
PS-ON debounce period. The voltage on PS-ON must be continuously present in a high or low state
for a minimum period for that state to be recognized.
–
t4:
Tdelay. The time from PS-ON being recognized as going high to MFAULT going high. This is to
provide a power down warning. When PS-ON requests power off, PW-OK goes low immediately.
–
t5:
UV blanking of DFAULT. During initial power up a period of UV blanking is applied to DFAULT as
soon as Vdd to the chip is in the correct range. No such blanking is applied to OV faults.
NORMAL OPERATION TIMING DIAGRAM (FIG. 18)
Figure 18. Normal Operation Timing Diagram (ON/OFF with PS-ON or the AC power switch).
AC
Vdd
PS-ON
Mfault
Main
OPs
POK
UVBmfault
ACsns
Off
On
On
Off
t3
t1
t2
t4
t3
t2
t1
Vdd-ok
UVBdfault
ACsns_high
ACsns_low
Vdd(on)
Vdd(on)
t5
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