L6710
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The voltage identification (VID*) pin configuration also sets the power-good thresholds (PGOOD) and the
Over / Under Voltage protection (OVP/UVP) thresholds.
The reference used for the regulation is also available externally on the pin REF_OUT; this pin must be
filtered vs. SGND with 47nF (typ.) ceramic capacitor to allow compatibility with VRD10.0 that is to allow
dynamic VID transitions that causes reference variations of 12.5mV / 5
Sec.
DYNAMIC VID TRANSITION
The device is able to manage Dynamic VID Code changes that allow Output Voltage modification during
normal device operation. The device checks on the clock rising and falling edge for VID code modifica-
tions. Once the new code is stable for at least one sample interval (half clock cycle) the reference steps
up or down in 12.5mV increments every clock cycle until the new VID code is reached. During the transi-
tion, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished.
PGOOD, OVP and UVP signals are masked during the transition and are re-activated after the transition
has finished.
DRIVER SECTION
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce
the RdsON), maintaining fast switching transition.
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers
for the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V
at VCCDRV pin is required to start operations of the device.
The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode con-
duction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to
few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously:
when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V,
the low-side mosfet gate drive is applied with 30ns delay.
When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the
high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the inductor is negative,
the source of high-side mosfet will never drop. To allow the turning on of the low-side mosfet even in this
case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than
240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate.
This mechanism allows the system to regulate even if the current is negative.
The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground
(SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The sepa-
rated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level
mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the appli-
cation. Power conversion is also flexible; 5V or 12V bus can be chosen freely.
The peak current is shown for both the upper and the lower driver of the two phases in figure 2. A 10nF
capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is
1.5A with VBOOT -VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink
current is 2A with VCCDR = 12V.