參數(shù)資料
型號(hào): L6728AHTR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, PDSO10
封裝: 3 X 3 MM, ROHS COMPLIANT, VFDFPN-10
文件頁(yè)數(shù): 11/33頁(yè)
文件大小: 1033K
代理商: L6728AHTR
L6728AH
Application information
Doc ID 15726 Rev 1
19/33
10.2
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output
and for the fast transient response of the power supply. They depend on the output voltage
ripple requirements, as well as any output voltage deviation requirement during a load
transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and
capacitive value of the output capacitors as follow:
Where
ΔI
L is the inductor current ripple. In particular, the expression that defines ΔVOUT_C
takes in consideration the output capacitor charge and discharge as a consequence of the
inductor current ripple.
During a load variation, the output capacitors supplies the current to the load or absorb the
current stored into the inductor until the converter reacts. In fact, even if the controller
recognizes immediately the load transient and sets the duty cycle at 80% or 0%, the current
slope is limited by the inductor value. The output voltage has a drop that also in this case
depends on the ESR and capacitive charge/discharge as follow:
Where
ΔV
L is the voltage applied to the inductor during the transient response
(
for the load appliance or VOUT for the load removal).
MLCC capacitors have typically low ESR to minimize the ripple but also have low
capacitance that do not minimize the voltage deviation during dynamic load variations. On
the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation
during load transients while they does not show the same ESR values of the MLCC resulting
then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC
capacitor is suggested to minimize ripple as well as reducing voltage deviation in dynamic
mode.
10.3
Input capacitors
The input capacitor bank is designed considering mainly the input RMS current that
depends on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as
follow:
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depends on the
input capacitor ESR and, in worst case, are:
ΔV
OUT_ESR
ΔI
L
ESR
=
ΔV
OUT_C
ΔI
L
1
8C
OUT
F
SW
---------------------------------------
=
ΔV
OUT_ESR
ΔI
OUT
ESR
=
ΔV
OUT_C
ΔI
OUT
L
ΔI
OUT
2C
OUT
ΔV
L
--------------------------------------
=
D
MAX
V
IN
V
OUT
I
rms
I
OUT
D1
D
()
=
PESR
I
OUT 2
()
2
=
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