
DEVICES INCORPORATED
L7C174
8K x 8 Cache-Tag Static RAM
03/26/1999–LDS.174-M
1
Special Architecture Static RAMs
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u 8K x 8 CMOS Static RAM with 8-bit
Tag Comparison Logic
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u High Speed Address-to-MATCH
— 12 ns maximum
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u High Speed Flash Clear
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u High Speed Read Access Time
— 12 ns maximum
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u Low Power Operation
Active: 300 mW typical at 35 ns
Standby: 500 W typical
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u Data Retention at 2 V for Battery
Backup Operation
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u Available 100% Screened to
MIL-STD-883, Class B
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u Plug Compatible with IDT7174,
IDT71B74, MK48H74
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u Package Styles Available:
28-pin Plastic DIP
28-pin Ceramic DIP
28-pin Plastic SOJ
32-pin Ceramic LCC
FEATURES
DESCRIPTION
L7C174
8K x 8 Cache-Tag Static RAM
DEVICES INCORPORATED
L7C174 BLOCK DIAGRAM
The L7C174 is a high-performance,
low power CMOS static RAM opti-
mized for use as the address tag
comparator in high speed cache
memory systems. One L7C174 can be
used to map 8K cache lines into a
1 megabyte address space by compar-
ing 20 address bits organized as
13-line address bits and 7-page
address bits.
The storage circuitry is organized as
8192 words by 8 bits per word and
includes an 8-bit data comparator
with MATCH output. The 8-bit data
is input/output on shared I/O pins
and comparison is performed between
8-bit incoming data and accessed
memory locations. Also provided is a
high speed CLEAR control which
clears all memory locations to zero
when activated. This allows all
address tag bits to be cleared when
powering on or when flushing the
cache.
This device is available in five speed
grades with maximum address-to-
MATCH times of 12 ns to 35 ns.
Operation is from a single +5 V power
supply with power consumption only
being 300 mW (typical) at 35 ns.
Dissipation drops to 500 W (typical)
when the memory is deselected
(Enable is high).
The L7C174 consumes only 30 W
(typical) at 3 V allowing effective
battery backup operation. For mini-
mal power consumption, data may be
retained in inactive storage with a
supply voltage as low as 2 V.
The L7C174 provides fully asynchro-
nous (unclocked) operation with
matching access and cycle times. An
active low Chip Enable and Output
Enable along with a three state I/O
bus simplify the connection of several
chips for increased storage capacity.
Wide tag addresses are easily accom-
modated by paralleling devices and
Wire-ORing the MATCH outputs. A
low on the MATCH output indicates a
data mismatch.
Memory locations are specified on
address pins A0 through A12 with
functions defined in the Truth Table.
During CLEAR, the state of the I/O
pins remain completely defined by the
WE, CE, and OE control inputs. Data
In has the same polarity as Data Out.
Latchup and static discharge protec-
tion are provided on-chip. The
L7C174 can withstand an injection
current of up to 200 mA on any pin
without damage.
ROW
ADDRESS
COLUMN SELECT
& COLUMN SENSE
5
COLUMN
ADDRESS
256 x 32 x 8
MEMORY
ARRAY
8
WE
OE
CE
ROW
SELECT
COMPARATOR
8
I/O7-0
CLEAR
MATCH
(OPEN DRAIN)
8
1 (if MATCH)
8
OBSOLETE