Data Sheet
July 2001
Forward Battery SLIC and Ringing Relay for TR-57 Applications
L9312 Line Interface and Line Access Circuit
Agere Systems Inc.
9
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
9
Symbol
LCF
Type
—
Name/Function
Loop Closure Filter Capacitor.
PPM injection can cause false loop closure indication.
Connect a capacitor from this node to V
CC
to filter the loop closure detector. If loop clo-
sure filtering is not required, leave this node open.
Battery Ground.
Ground return for the battery supply.
Auxiliary Battery.
If a lower-voltage auxiliary battery is used, connect the auxiliary bat-
tery supply to this node. If a power control resistor is used, connect the power control
resistor from this node to V
BAT1
. If no power control technique is used, connect this node
to V
BAT1
.
Office Battery Supply.
Negative high-voltage power supply.
Office Battery Supply.
Negative high-voltage power supply.
Battery Ground.
Ground return for the battery supply.
Connect to V
REF
.
Connect to V
REF
.
Ring Trip Sense.
Sense input for the ring trip detector.
Ring Lead Ringing Access Switch.
Ringing relay connects this pin to pin RRING. Con-
nect this pin to pin PR through a 400
current-limiting resistor.
Ringing Access.
Input to solid-state ringing access switch. Connect to ringing genera-
tor.
Protected Ring.
The output of the ring driver amplifier and input to loop sensing con-
nected through solid-state break switch. Connect to subscriber loop through overvolt-
age/current protection.
Protected Tip.
The output of the tip driver amplifier and input to loop sensing connected
through solid-state break switch. Connect to subscriber loop through overvoltage/cur-
rent protection.
Tip Ringing Return.
Ring relay connects this pin to PT. Connect to ringing supply
return.
Loop Status.
The output of the loop status detector (loop start detector wired-OR with
ring trip detector). This loop status supervision output is not controlled by the data latch.
Digital Ground.
Ground return for V
DD
current.
Data Control Input.
See Table 2, Control States, for details.
Data Control Input.
See Table 2, Control States, for details.
Data Control Input.
See Table 2, Control States, for details.
Reset.
A logic low will override the B[0:3] and LATCH inputs and reset the state of the
SLIC to the disconnect state and the switch to the all-off state.
Latch Control Input.
Edge-level sensitive control for data latches.
5 V Digital Power Supply.
5 V supply for digital circuitry.
Digital Ground.
Ground return for V
DD
current.
Analog Ground.
Tip/Ring Voltage Output.
This output is a voltage that is directly proportional to the dif-
ferential tip/ring current. A resistor from this node to ITR sets the device transimped-
ance. Gain shaping for termination impedance with a COMBO I codec is also achieved
with a network from this node to ITR.
10
11
BGND
RPWR
G
P
12
13
14
15
16
19
20
V
BAT1
V
BAT1
BGND
TIE B’
TIE A’
RTS
RSW
P
P
G
—
—
I
O
21
RRING
I
22
PR
I/O
23
PT
I/O
24
TRING
O
25
NSTAT
O
26
27
28
29
30
DGND
B2
B1
B0
RESET
G
I
I
I
I
31
32
33
35
36
LATCH
V
DD
DGND
AGND
VTX
I
P
G
G
O