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參數(shù)資料
| 型號： | LA4032V-75TN44E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 2/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 32MACROCELLS 44TQFP |
| 標準包裝： | 160 |
| 系列： | LA-ispMACH |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 30 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can
also be congured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:
LVTTL
LVCMOS 1.8
LVCMOS 3.3
3.3V PCI Compatible
LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
congured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually congured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
GOE 0
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
GOE 1
GOE 2
GOE 3
VCC
VCCO
**
*
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LA4032V-75TN48E | 功能描述:CPLD - 復雜可編程邏輯器件 Auto Grade (AEC-Q100 ) ispMACH4032V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LA4032ZC-75TN100E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN128E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN144E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN44E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
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