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參數(shù)資料
| 型號： | LA7578 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 252K |
| 代理商： | LA7578 |
Fig. 26
Fig. 27
C
eramic BPF
pin 24
(A) Good example
Ceramic BPF
(B) Bad example
Fig. 28
Pin 24
BPF input and output are close
to each other.
Designing the external bleeder resistance ratio so that
the output DC voltage (V21) does not change when
the voltage is amplified by the equalizer amplifier
Assuming the desired gain is Av, then to make Vx
6
V21 so
that the sync signal voltage does not change:
Vx = V
CC
×
R2/(R2 + R3) ................. : (1)
From the desired voltage gain:
Av = 1 + 1 k/Z1 .................................. : (2)
Z1 = R2
×
R3/(R2 + R3) .................... : (3)
And then:
R2 = 1 k
×
V
CC
/[(V
CC
Vx)
×
(Av1)] ............: (4)
R3 = 1 k
×
V
CC
/[(Av 1)
×
Vx] ........................: (5)
These simple calculations can be used to design the ratio.
Pin 22 (GND)
Connected to GND within the IC.
Pin 23 (GND)
Connected to GND within the IC.
Pin 24 (SIF input)
This is the SIF input pin.
The input impedance is approximately 1 k
. If an interfering
wave (video signal, etc.) flows into this input, it will generate a
buzz or buzz beat; therefore, caution must be exercised in
regard to the pattern layout for the input circuit. Fig. (B) below
shows a bad example.
LA7578N
No.4037-16/18
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