參數(shù)資料
型號： LAMXO2280E-3FTN324E
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 8/77頁
文件大?。?/td> 0K
描述： IC FPGA AUTO 2.28KLUTS 324-BGA
標(biāo)準(zhǔn)包裝： 84
系列： LA-MachXO
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 5.1ns
電壓電源 - 內(nèi)部： 1.14 V ~ 1.26 V
宏單元數(shù)： 1140
輸入/輸出數(shù)： 271
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-FTBGA（19x19）
包裝： 托盤
2-13
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Figure 2-13. Memory Core Reset
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the
EBR is always asynchronous.
Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during conguration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-
nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing
rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and
RPReset are always asynchronous EBR inputs.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Q
SET
D
LCLR
Output Data
Latches
Memory Core
Port A[17:0]
Q
SET
D
Port B[17:0]
RSTB
GSRN
Programmable Disable
RSTA
LCLR
Reset
Clock
Enable
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