參數(shù)資料
型號： LAMXO2280E-3TN100E
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 76/77頁
文件大小： 0K
描述： IC FPGA AUTO 2.28KLUTS 100-TQFP
標準包裝： 90
系列： LA-MachXO
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 5.1ns
電壓電源 - 內(nèi)部： 1.14 V ~ 1.26 V
宏單元數(shù)： 1140
輸入/輸出數(shù)： 73
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-TQFP（14x14）
包裝： 托盤
2-5
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic Mode: In this mode, the LUTs in each Slice are congured as 4-input combinatorial lookup tables (LUT4). A
LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by program-
ming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger
lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efcient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Ripple mode multiplier building block
Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the
software will construct these using distributed memory primitives that represent the capabilities of the PFU.
Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows
the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice
functions as the read-write port, while the other companion Slice supports the read-only port. For more information
on RAM mode in LA-MachXO devices, please see details of additional technical documentation at the end of this
data sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
Logic
Ripple
RAM
ROM
PFU Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
SP 16x2
ROM 16x1 x 2
PFF Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
N/A
ROM 16x1 x 2
SPR16x2
DPR16x2
Number of Slices
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
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