參數(shù)資料
型號: LAN9116-MD
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 50/126頁
文件大?。?/td> 831K
代理商: LAN9116-MD
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
50
SMSC LAN9116
DATASHEET
3.12.6.2
TX Example 2
In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer
as follows:
2-Byte “Data Start Offset”
183-Bytes of payload data
4-Byte “Buffer End Alignment”
Figure 3.15, "TX Example 2" illustrates the TX command structure for this example, and also shows
how data is passed to the TX data FIFO. Note that the packet resides in a single TX Buffer, therefore
both the FS and LS bits are set in TX command ‘A’.
Figure 3.15 TX Example 2
TX Command 'A'
0
31
TX Command 'B'
Data Written to the
Ethernet Controller
TX Command 'B'
183-Byte Payload Data
Data Start Offset = 6
First Segment = 1
Last Segment = 1
Buffer Size =183
Packet Length = 183
TX Command 'A'
Buffer End Alignment = 0
TX Command 'B'
Data Passed to the
TX Data FIFO
3B End Padding
TX Command 'A'
6-Byte Data Start Offset
183-Byte Payload Data
NOTE: Extra bytes between buffers
are not transmitted
相關(guān)PDF資料
PDF描述
LAN9116-MT Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
LP621024D-55LLT 128K X 8 BIT CMOS SRAM
LP621024D-I 128K X 8 BIT CMOS SRAM
LP621024D-T 128K X 8 BIT CMOS SRAM
LP62S1024BM-70LLT 128K X 8 BIT LOW VOLTAGE CMOS SRAM
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