參數(shù)資料
型號： LAN9116-MD
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 71/126頁
文件大?。?/td> 831K
代理商： LAN9116-MD
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
71
Revision 1.1 (05-17-05)
DATASHEET
5.3.4
INT_EN—Interrupt Enable Register
This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the
corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of
the interrupt source regardless of whether the source is enabled as an interrupt in this register.
12
Reserved
RO
-
11
TX Data FIFO Underrun Interrupt (TDFU).
Generated when the TX data
FIFO underruns.
R/WC
0
10
TX Data FIFO Overrun Interrupt (TDFO).
Generated when the TX data
FIFO is full, and another write is attempted.
R/WC
0
9
TX Data FIFO Available Interrupt (TDFA).
Generated when the TX data
FIFO available space is greater than the programmed level.
R/WC
0
8
TX Status FIFO Full Interrupt (TSFF).
Generated when the TX Status
FIFO is full.
R/WC
0
7
TX Status FIFO Level Interrupt (TSFL).
Generated when the TX Status
FIFO reaches the programmed level.
R/WC
0
6
RX Dropped Frame Interrupt (RXDF_INT).
This interrupt is issued
whenever a receive frame is dropped.
R/WC
0
5
RX Data FIFO Level Interrupt (RDFL).
Generated when the RX FIFO
reaches the programmed level.
R/WC
0
4
RX Status FIFO Full Interrupt (RSFF).
Generated when the RX Status
FIFO is full.
R/WC
0
3
RX Status FIFO Level Interrupt (RSFL).
Generated when the RX Status
FIFO reaches the programmed level.
R/WC
0
2-0
GPIO [2:0] (GPIOx_INT).
Interrupts are generated from the GPIO’s.
These interrupts are configured through the GPIO_CFG register.
R/WC
000
Offset:
5Ch
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
Software Interrupt (SW_INT_EN)
R/W
0
30:26
Reserved
RO
-
25
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
R/W
0
24
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
R/W
0
23
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN).
R/W
0
22
Reserved
RO
0
21
TX IOC Interrupt Enable (TIOC_INT_EN)
R/W
0
20
RX DMA Interrupt (RXD_INT).
R/W
0
19
GP Timer (GPT_INT_EN)
R/W
0
BITS
DESCRIPTION
TYPE
DEFAULT
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LAN9116-MT Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
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