參數(shù)資料
型號: LAN9117-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 75/131頁
文件大?。?/td> 1531K
代理商: LAN9117-MT
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.3
SMSC LAN9117
75
Revision 1.1 (05-17-05)
DATASHEET
INT_STS—Interrupt Status Register
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding
bits acknowledges and clears the interrupt.
Offset:
58h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
Software Interrupt (SW_INT).
This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
R/WC
0
30-26
Reserved
RO
-
25
TX Stopped (TXSTOP_INT).
This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
R/WC
0
24
RX Stopped (RXSTOP_INT).
T
his interrupt is issued when the receiver is
halted.
R/WC
0
23
RX Dropped Frame Counter Halfway (RXDFH_INT).
This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
R/WC
0
22
Reserved
RO
0
21
TX IOC Interrupt (TX_IOC).
When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
R/WC
0
20
RX DMA Interrupt (RXD_INT).
This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
R/WC
0
19
GP Timer (GPT_INT).
This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
R/WC
0
18
PHY (PHY_INT).
Indicates a PHY Interrupt event.
RO
0
17
Power Management Event Interrupt (PME_INT).
This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1'
clears this bit regardless of the state of the PME hardware signal.
Notes:
Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9117. The LAN9117 will only wake up
when it detects a host write cycle of any data to the BYTE_TEST
register.
The Interrupt Deassertion interval does not apply to the PME interrupt.
R/WC
0
16
TX Status FIFO Overflow (TXSO).
Generated when the TX Status
FIFO overflows.
R/WC
0
15
Receive Watchdog Time-out (RWT).
Interrupt is generated when a
packet larger than 2048 bytes has been received.
R/WC
0
14
Receiver Error (RXE).
Indicates that the receiver has encountered an
error. Please refer to
Section 3.14.5, "Receiver Errors," on page 61
for a
description of the conditions that will cause an RXE.
R/WC
0
13
Transmitter Error (TXE).
When generated, indicates that the
transmitter has encountered an error. Please refer to
Section 3.13.8,
"Transmitter Errors," on page 56
, for a description of the conditions that
will cause a TXE.
R/WC
0
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