參數(shù)資料
型號(hào)： LAN91C100FD
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網(wǎng)控制器以全雙工能力
文件頁(yè)數(shù)： 56/79頁(yè)
文件大?。?/td> 585K
代理商： LAN91C100FD
FEAST Fast Ethernet Controller with Full Duplex Capability
Rev.
10/14/2002
Page 56
SMSC DS – LAN91C100FD Rev. D
PRELIMINARY
Chapter 7 Application Considerations
The LAN91C100FD is envisioned to fit a few different bus types. This section describes the basic
guidelines, system level implications and sample configurations for the most relevant bus types. All
applications are based on buffered architectures with a private SRAM bus.
7.1
Fast Ethernet Slave Adapter
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
a) LAN91C100FD chip
b) Four SRAMs (32k x 8 - 25ns)
c) Serial EEPROM (93C46)
d) Mbps ENDEC and transceiver chip
e) Mbps MII compliant PHY
f)
Some bus specific glue logic
Target systems:
a) VL Local Bus 32 bit systems
b) High-end ISA or non-burst EISA machines
c) EISA 32 bit slave
7.2
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed as a 32 bit
peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using
byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions.
Table 7.1 - VL Local Bus Signal Connections
VL BUS
SIGNAL
A2-A15
LAN91C100
SIGNAL
A2-A15
NOTES
Address bus used for I/O space and register decoding, latched
by nADS rising edge, and transparent on nADS low time.
Qualifies valid I/O decoding - enabled access when low. This
signal is latched by nADS rising edge and transparent on nADS
low time.
Direction of access. Sampled by the LAN91C100FD on first
rising clock that has nCYCLE active. High on writes, low on
reads.
Ready return. Direct connection to VL bus.
nSRDY has the appropriate functionality and timing to create the
VL nLRDY except that nLRDY behaves like an open drain output
most of the time.
Local Bus Clock. Rising edges used for synchronous bus
interface transactions.
Connected via inverter to the LAN91C100FD.
M/nIO
AEN
W/nR
W/nR
nRDYRTN
nLRDY
nRDYRTN
nSRDY and
some logic
LCLK
LCLK
nRESET
RESET
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