LB11823M
No.7106-14/18
13. Brake operation
Braking is made by setting the BR pin to the L level. Braking consists of a short-circuit brake condition in which all of
one-side outputs (UH, VH, or WH) are turned ON while other outputs (UL, VL, WL) are turned OFF. A measure is
taken to prevent flow of through current (through current due to output Tr OFF delay time at selection) when the brake
is operated or cancelled. While braking is made, current limiting and motor lock protection circuits are not operative.
Short-circuit braking causes large current to flow through the output Tr because of motor coil resistance and the motor
reverse electromotive voltage condition during operation. It is therefore necessary to select the external output Tr that is
not damaged by this current or to activate braking only when the motor rotation speed has decreased to a certain level.
14. Power supply stabilization
This IC is of a switching drive type and the power line tends to be affected. It is therefore necessary to connect a
capacitor of sufficient capacity for stabilization between the VCC1 pin and GND.
To insert a diode in the power line to prevent breakdown through reverse connection of power supply, the power line
becomes more readily affected. It is necessary to select a larger capacity.
To turn ON/OFF the power supply with a switch, etc., large distance between the switch and capacitor causes
substantial deviation of the supply voltage due to the line inductance and inrush current into the capacitor. In certain
cases, the withstand voltage may be exceeded. In this case, do not use a ceramic capacitor whose series impedance is
low. Instead, use an electrolytic capacitor to suppress the inrush current and to prevent voltage rise.
15. VREG stabilization
To stabilize the VREG voltage that is the power supply for the control circuit, connect a 0.1
μF or more capacitor
between VREG and GND. The capacitor GND must be wired near the GND pin of IC as much as possible.
16. FG amplifier
Considering connection of the Hall device output, etc., the FG amplifier input does not incorporate the bias voltage. To
enter pattern FG, etc., it is necessary to apply the bias voltage to the FGIN+ pin (by applying the VREG/2 voltage
determined through division with resistor from VREG, etc.).
There are a Schmidt comparator and filter circuit after the FG amplifier output, so that the noise is not readily included
in the FGS output. FGOUT and FGS have the same logic.