參數(shù)資料
型號: LB11872H
元件分類: 運動控制電子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 1.2 A, PDSO30
封裝: HSOP-28/30
文件頁數(shù): 5/11頁
文件大小: 125K
代理商: LB11872H
LB11872H
No.7257-3/11
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Phase comparator output
High-level output voltage
VPDH
IOH = -100μA
VREG-0.2
VREG-0.1
V
Low-level output voltage
VPDL
IOL = 100μA
0.2
0.3
V
Output source current
IPD+
VPD = VREG/2
-500
μA
Output sink current
IPD-
VPD = VREG/2
1.5
mA
Lock detection output
Output saturation voltage
VLD (SAT)
ILD = 10mA
0.15
0.5
V
Output leakage current
ILD (LEAK)
VLD = 28V
10
μA
FG output
Output saturation voltage
VFG (SAT)
IFG = 5mA
0.15
0.5
V
Output leakage current
IFG (LEAK)
VFG = 28V
10
μA
Drive block
Dead zone width
VDZ
With the phase is locked
50
100
300
mV
Output idling voltage
VID
6
mV
Forward gain 1
GDF+1
With phase locked
0.4
0.5
0.6
Times
Forward gain 2
GDF+2
With phase unlocked
0.8
1.0
1.2
Times
Reverse gain 1
GDF-1
With phase locked
-0.6
-0.5
-0.4
Times
Reverse gain 2
GDF-2
With phase unlocked
-0.8
-1.0
-1.2
Times
Acceleration command voltage
VSTA
5.0
5.6
V
Deceleration command voltage
VSTO
0.8
1.5
V
Forward limiter voltage
VL1
Rf = 22
Ω
0.53
0.59
0.65
V
Reverse limiter voltage
VL2
Rf = 22
Ω
0.32
0.37
0.42
V
CSD oscillator circuit
Oscillation frequency
fOSC
C = 0.022
μF
31
Hz
High-level pin voltage
VCSDH
4.3
4.8
5.3
V
Low-level pin voltage
VCSDL
0.75
1.15
1.55
V
External capacitor charge and
discharge current
ICHG
35
7
μA
Lock detection delay count
CSDCT1
7
Clock cutoff protection operating
count
CSDCT2
2
Lock protection count
CSDCT3
31
Initial reset voltage
VRES
0.60
0.80
V
Clock input block
External input frequency
fCLK
400
10000
Hz
High-level input voltage
VIH (CLK)
Design target value*1
2.0
VREG
V
Low-level input voltage
VIL (CLK)
Design target value*1
0
1.0
V
Input open voltage
VIO (CLK)
2.7
3.0
3.3
V
Hysteresis width
VIS (CLK)
Design target value*1
0.1
0.2
0.3
V
High-level input current
IIH (CLK)
V (CLK) = VREG
140
185
μA
Low-level input current
IIL (CLK)
V (CLK) = 0V
-185
-140
μA
S/S pin
High-level input voltage
VIH (S/S)
2.0
VREG
V
Low-level input voltage
VIL (S/S)
0
1.0
V
Input open voltage
VIO (S/S)
2.7
3.0
3.3
V
Hysteresis width
VIS (S/S)
0.1
0.2
0.3
V
High-level input current
IIH (S/S)
V (S/S) = VREG
140
185
μA
Low-level input current
IIL (S/S)
V (S/S) = 0V
-185
-140
μA
*1 : This parameter is a design target value and is not measured.
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