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參數(shù)資料
| 型號： | LB1870 |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 1 A, PDIP28 |
| 封裝： | HSDIP-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | LB1870 |
Continued from preceding page.
No. 4356-3/11
LB1870, 1870M
Parameter
Symbol
Conditions
min
typ
max
Unit
[Error amplifier]
Input offset voltage
VIO (ER)
Design target value
–10
+10
mV
Input bias current
IB (ER)
–1
+1
A
DC bias level
VB (ER)
–5%
1/2 VREG
+5%
V
Output high level voltage
VOH (ER)
No external load
VREG – 1.0
V
Output low level voltage
VOL (ER)
No external load
1.0
V
[Phase comparator output]
Output high level voltage
VPDH
No external load
VREG – 0.4
V
Output low level voltage
VPDL
No external load
0.4
V
Output source current
IPD+
VPD = VREG/2
–0.6
mA
Output sink current
IPD–
VPD = VREG/2
1.5
mA
[Lock detector output]
Output saturation voltage
VLD (sat)
ILD = 5 mA
0.1
0.4
V
Output leakage current
ILD (LEAK) VCC = 28 V
10
A
[Drive block]
Dead zone
VDZ
50
100
300
mV
Output idling voltage
VID
6mV
Forward gain
GDF+
0.4
0.5
0.6
Reverse gain
GDF–
–0.6
–0.5
–0.4
Accelerate command voltage
VSTA
5.0
5.6
V
Decelerate command voltage
VSTO
0.8
1.5
V
Forward limiter voltage
VL+
Rf = 22
0.58
V
Reverse limiter voltage
VL–
Rf = 22
0.58
V
[Reference signal block]
Crystal oscillator frequency
fOSC
Crystal oscillator mode
1
8
MHz
Low level pin voltage
VOSCL
IOSC = –0.5 mA
4.4
V
High level pin voltage
IOSCH
VOSC = VOSCL + 0.3 V
0.5
mA
[External clock input block]
External input frequency
fCLK
External clock mode
500
7000
Hz
Input high level voltage
VIH (CLK)
3.5
VREG
V
Input low level voltage
VIL (CLK)
0
+1.5
V
Input open voltage
VIO (CLK)
3.5
4.0
4.7
V
Hysteresis
VIS (CLK)
0.27
0.4
0.53
V
Input high level current
IIH (CLK)
V (CLK) = VREG
155
200
A
Input low level current
IIL (CLK)
V (CLK) = 0 V
–400
–300
A
[N1 pin]
Input high level voltage
VIH (N1)
3.5
VREG
V
Input low level voltage
VIL (N1)
0
+1.5
V
Input open voltage
VIO (N1)
3.5
4.0
4.7
V
Input high level current
IIH (N1)
V (N1) = VREG
155
200
A
Input low level current
IIL (N1)
V (N1) = 0 V
–400
–300
A
[N2 pin]
Input high level voltage
VIH (N2)
4.0
VREG
V
Input middle level voltage
VIM (N2)
2.0
3.0
V
Input low level voltage
VIL (N2)
0
+1.0
V
Input open voltage
VIO (N2)
3.5
4.0
4.7
V
Input high level current
IIH (N2)
V (N2) = VREG
155
200
A
Input low level current
IIL (N2)
V (N2) = 0 V
–400
–300
A
[S/S pin]
Input high level voltage
VIH (S/S)
3.5
VREG
V
Input low level voltage
VIL (S/S)
0
+1.5
V
Input open voltage
VIO (S/S)
3.5
4.0
4.7
V
Hysteresis
VIS (S/S)
0.27
0.4
0.53
V
Input high level current
IIH (S/S)
V (S/S) = VREG
155
200
A
Input low level current
IIL (S/S)
V (S/S) = 0 V
–400
–300
A
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