- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19766 > LC5256MB-75FN256C (Lattice Semiconductor Corporation)IC CPLD 256MACROCELLS 256FPBGA PDF資料下載
參數(shù)資料
| 型號： | LC5256MB-75FN256C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 2/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 256MACROCELLS 256FPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispXPLD® 5000MB |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 2.3 V ~ 2.7 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 256 |
| 輸入/輸出數(shù)： | 141 |
| 工作溫度： | 0°C ~ 90°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
| 包裝： | 托盤 |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
6
AND-Array
The programmable AND-Array consists of 68 inputs and 164 output product terms. The 68 inputs from the GRP are
used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 164 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-
OR Array with the remaining four control product terms feeding the Shared PT Clock, Shared PT Clock Enable,
Shared PT Reset and Shared PT OE. Starting with PT0 sets of five product terms form product term clusters.
There is one product term cluster for every macrocell in the MFB. In addition to the four control product terms, the
first, third, fourth and fifth product terms of each cluster can be used as a PTOE, PT Clock, PT Preset and PT
Reset, respectively. Figure 5 is a graphical representation of the AND-Array.
Figure 5. AND Array
Dual-OR Array (Including Arithmetic Support)
The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the MFB. These OR gates
are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate
receives its five inputs from the combination of product terms associated with the product term cluster. The PTSA-
Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable PTSA OR gate receives five
inputs from the combination of product terms associated with the product term cluster. It also receives an additional
input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number of the macrocell associated
with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing with other product terms and
the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for wide functions. There is a
small timing adder for each level of expansion. Figure 6 is a graphical representation of the Dual-OR Array.
The Dual-OR PT sharing array also contains logic to aid in the efficient implementation of arithmetic functions. This
logic takes Carry In and allows the generation of Carry Out along with a SUM signal. Subtractors can be imple-
mented using the two’s complement method. Carry is propagated from macrocells 0 to macrocell 31. Macrocell
zero can have its carry input connected to the carry output of macrocell 31 in an adjacent MFB or it can be set to
zero or one. If a macrocell is not used in an arithmetic function carry can bypass it. The carry chain flows is the
same as that for PT cascading.
PT0
PT1
Cluster 0
PT2
PT3
PT4
In[0]
In[66]
In[67]
Note:
Indicates programmable fuse.
PT160 Shared clock enable
PT162
PT163
Shared reset
Shared OE
PT156
PT157
PT158
PT159
PT155
Cluster 31
PT161 Shared clock
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B5Y-CX-F2 | CONVERTER MOD DC/DC 3.3V 49.5W |
| REC3-2409SRW/H/B | CONV DC/DC 3W 18-36VIN 09VOUT |
| A151J15C0GK5UAA | CAP CER 150PF 200V 5% NP0 AXIAL |
| REC3-2405DR/H1/M | CONV DC/DC 3W 24VIN +/-05VOUT |
| REC3-123.3SRW/H/B | CONV DC/DC 3W 9-18VIN 3.3VOUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC5256MB-75FN256I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5256MB-75FN484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MB-75FN484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MB-75FN672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MB-75FN672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。