參數(shù)資料
型號： LC5512MV-45FN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 7/99頁
文件大小： 0K
描述： IC CPLD 512MACROCELLS 484FPBGA
標準包裝： 60
系列： ispXPLD® 5000MV
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 4.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 253
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
包裝： 托盤
其它名稱： 220-1726
LC5512MV-45FN484C-ND
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
11
Pseudo Dual-Port SRAM Mode
In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Register
Input
Source
Write Address, Write
Data, Write Enable,
and Write Chip Select
Clock
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
Clock Enable
WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
Read Data and Read
Address
Clock
RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be
inverted if desired.
Clock Enable
RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
‘
68 Inputs
From
Routing
16,384 bit
Pseudo
Dual
Port
SRAM
Array
Write Address
(WAD[0:8-13])
Write Clk Enable (WCEN)
Write Clock (WCLK)
Read Address
(RAD[0:8-13])
Write Enable (WE)
Write Chip Sel (WCS[0,1])
Reset (RST)
Read Clk Enable (RCEN)
Read Clock (RCLK)
Write Data
(WD[0:0,1,3,7,15,31])
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(RD[0:0-15])
SELECT
DEVICES
DISCONTINUED
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參數(shù)描述
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LC5512MV-45FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-45Q208C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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