參數(shù)資料
型號: LC5512MV-45QN208C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 74/99頁
文件大?。?/td> 0K
描述: IC CPLD 512MACROCELLS 208PQFP
標準包裝: 24
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 4.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 512
輸入/輸出數(shù): 149
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
72
3
76P
L30/PLL_FBK1
L0
J0
L31
F15
E21
3
77N
M0/PLL_RST1
P27
N27
M1
H12
G22
3
77P
M2
P26N26
M3
G14F21
-
GND (Bank 3)
-
GND (Bank 3) GND (Bank 3)
3
78N
M4
P25
N25
M5
F16
H21
-
VCCO3
-
VCCO3
3
78P
M6
P24
N24
-
E16
G21
-
GND
-
GND
3
79N
M8
P23
N23
M9
G13
D22
3
79P
M10
P22
N22
M11
G12
D21
3
80N
M12
P21
N21
M13
F14
J20
3
80P
M14/CLK_OUT1
P20
N20
M15
E15
J19
3
81N
M16
N31
-
M17
F12
E20
-
VCC
-
VCC
3
81P
M18
N30
M30
M19
F13
F20
3
82N
M20
N29
M28
M21
D16
H17
3
82P
M22
N28
M26
M23
D15
H18
-
GND (Bank 3)
-
GND (Bank 3) GND (Bank 3)
3
83N
M24
N27
-
M25
J18
-
VCCO3
-
VCCO3
3
83P
M26
N26
-
M27
H19
3
84N
M28
N25
-
M29
G20
3
84P
M30
N24
-
M31
G19
-
GND
-
GND
3
85N
N0
N23
-
N1
C22
-
VCC
-
VCC
3
85P
N2
N22
-
N3
C21
3
86N
N4
N21
-
D20
3
86P
N6
N20
-
C19
3
87N
N8
N19
-
N9
C16
F19
3
87P
N10
N18
-
N11
B16
E19
-
GND (Bank 3)
-
GND (Bank 3) GND (Bank 3)
3
88N
N12
N17
-
N13
C15
G18
-
VCCO3
-
VCCO3
3
88P
N14
N16
-
N15
B15
F18
3
89N
N16
N15
-
N17
E14
B20
3
89P
N18
N14
-
N19
D14
B19
3
90N
N20
N13
-
N21
E13
A20
3
90P
N22
N12
-
N23
A15
A19
3
91N
N24
P19
N19
N25
D12
D18
3
91P
N26
P18
N18
N27
B14
C18
3
92N
N28
P17
N17
N29
C13
G17
3
92P
N30
P16
N16
N31
A14
F16
ispXPLD 5768MX Logic Signal Connections (Continued)
sysIO Bank LVDS Pair
Primary Macrocell/
Function
Alternate Outputs
Alternate
Inputs
256 fpBGA
Ball Number
484 fpBGA
Ball Number
Macrocell 1
Macrocell 2
SELECT
DEVICES
DISCONTINUED
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