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參數(shù)資料
| 型號： | LC7153M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 279K |
| 代理商： | LC7153M |
LC7153, 7153M
No.4160–6/11
The phase-detector secondary output is high impedance
when the PLL is locked. In this case, R1 becomes R1M,
Figure 1. Dual charge-pump circuit
increasing the LPF time constant and improving sideband
and modulation response.
Test Mode
TEST should be LOW or open for normal operation.
Serial Input Data
Serial data should be input only after fXIN has become
stable.
Mode 1 command format and functions
The Mode 1 command comprises the data bits which de-
termine the PLLA and PLLB programmable divider ratios.
The command format is shown in figure 2. Bits DA0 to
DA15 and DB0 to DB15 determine the PLLA and PLLB
programmable divider ratios, respectively. Bit DA0 is the
first bit received. The range of allowable divider ratios is N
=256 (0100H) to 65535 (FFFFH).
Figure 2. Mode 1 command (programmable divider data)
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