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參數(shù)資料
| 型號： | LC72121M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 377K |
| 代理商： | LC72121M |
Other Items
Notes on the phase comparator dead zone
When the charge pump is used with one of the ON/ON modes, correction pulses are generated from the charge pump
even if the PLL is locked. As a result, it is easy for the loop to become unstable, and special care is required in
application design. The following problems can occur if an ON/ON mode is used.
— Sidebands may be created by reference frequency leakage.
— Sidebands may be created by low-frequency leakage due to the correction pulse envelope.
Although the loop is more stable when a dead zone is present (i.e. when an OFF/OFF mode is used), a dead zone
makes it more difficult to achieve excellent C/N characteristics. On the other hand, while it is easy to achieve good C/N
characteristics when there is no dead zone, achieving good loop stability is difficult. Accordingly, the DZA and DZB
settings, in which there is no dead zone, can be effective in situations where a signal-to-noise ratio of 90 to 100 dB or
higher is required in FM reception, or where it is desirable to increase the pilot margin in AM stereo reception.
However, if such a high signal-to-noise ratio is not required for FM reception, if an adequate pilot margin can be
acquired in AM stereo reception, or if AM stereo is not required, then either DZC or DZD, in which there is a dead
zone, should be chosen.
Dead Zone
As shown in figure 1, the phase comparator compares a reference frequency (fr) with fp. As shown in figure 2, the phase
comparator's characteristics consist of an output voltage (V) that is proportional to the phase difference . However, due
to internal circuit delay and other factors, an actual circuit has a region (the dead zone, B) where the circuit cannot
actually compare the phases. To implement a receiver with a high S/N ratio, it is desirable that this region be as small as
possible. However, it is often desirable to have the dead zone be slightly wider in popularly-priced models. This is
because in certain cases, such as when there is a strong RF input, popularly-priced models can suffer from mixer to VCO
RF leakage that modulates the VCO. When the dead zone is small, the circuit outputs signals to correct this modulation
and this output further modulates the VCO. This further modulation may then generate beats and the RF signal.
Notes on the FMIN, AMIN, and IFIN pins
Coupling capacitors should be placed as close to their pin as possible. A capacitance of about 100 pF is desirable for
these capacitors. In particular, if the IFIN pin coupling capacitor is not held under 1000 pF, the time to reach the bias
level may become excessive and incorrect counts may result due to the relationship with the wait time.
Notes on IF counting
→ Use the SD signal in conjunction with IF counting
When counting the IF frequency, the microcontroller must determine the presence or absence of the IF IC SD (station
detect) signal and turn on the IF counter buffer output and execute the IF count only if there is an SD signal. Auto-
search techniques that only use the IF counter are subject to incorrect stopping at points where there is no station due to
IF buffer leakage.
No. 5815-21/23
LC72121, 72121M, 72121V
DZ1
DZ0
Dead zone mode
Charge pump
Dead zone
0
DZA
ON/ON
– –0s
0
1
DZB
ON/ON
–0s
1
0
DZC
OFF/OFF
+0s
1
DZD
OFF/OFF
+ +0s
Figure 1
Figure 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72121MA | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC PLL Frequency Synthesizers for Electronic Tuning |
| LC72121MA-AH | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72121MV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC72121V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers for Electronic Tuning |
| LC72121V-D-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
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