參數(shù)資料
型號: LC72121M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24
封裝: MFP-24
文件頁數(shù): 9/23頁
文件大?。?/td> 377K
代理商: LC72121M
Unlocked State Detection Timing
Unlocked state detection timing
Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period
at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However,
applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N)
before checking the locked/unlocked state.
No. 5815-17/23
LC72121, 72121M, 72121V
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz (a period of 1 ms) applications must wait at least 2 ms after the divisor N is changed
before performing a locked/unlocked check.
Figure 2 Circuit Structure
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