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參數(shù)資料
| 型號： | LC72136NM |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 318K |
| 代理商： | LC72136NM |
No. 5608-12/23
LC72136N, 72136NM
Continued from preceding page.
DO Output Data (Serial Data Output) Structure
3. OUT mode
DO Output Data
No.
Control block/data
Description
Related data
IF counter control data
This data should be set to 1 in normal operation. Setting this data to 0 switches
(11)
IFS
the LC72136N to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
* See the “IF Counter Operation” item for details.
LSI test data
LSI test data
TEST 0 to TEST3
TEST0
(12)
TEST1
All three bits must be set to 0.
TEST2
All the test data is set to 0 following a power-on reset.
No.
Control block/data
Description
Related data
I/O port data
Data latched from the states of the I/O ports, pins IO1 and IO2.
I2, I1
This data reflects the pin states, regardless of whether they are in input or output mode.
The data is latched when OUT mode is selected.
I1
← IO1 pin state
High: 1
I2
← IO2 pin state
Low: 0
PLL unlock data
Data latched from the state of the unlock detection circuit
UL
← 0: Unlocked
UL
← 1: Locked or in detection stopped mode
IF counter binary data
Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19 to C0
C19
← Binary counter MSB
C0
← Binary counter LSB
(1)
(2)
(3)
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
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