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參數資料
| 型號： | LC72136NM |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數： | 7/23頁 |
| 文件大小： | 318K |
| 代理商： | LC72136NM |
No. 5608-15/23
LC72136N, 72136NM
Programmable Divider Structure
Note: * Don’t care.
Sample Programmable Divider Divisor Calculations
1. For a 50 kHz FM step size (DVS = 1, SNS = *: FMIN selected)
FM RF = 90.0 MHz (IF = +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
100.7 MHz (FM VCO)
÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 2014 → 07DE (HEX)
2. For a 5 kHz SW step size (DVS = 0, SNS = 1: AMIN high-speed side selected)
SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO)
÷ 5 kHz (fref) = 4440 → 1158 (HEX)
3. For a 9 kHz MW step size (DVS = 0, SNS = 0: AMIN low-speed side selected)
MW RF = 1008 kHz (IF = +450 kHz)
MW VCO = 1458 kHz
PLL fref = 3 kHz (R0 to R1 = 0, R2 to R3 = 1): using a 3 kHz reference frequency
1458 kHz (MW VCO)
÷ 3 kHz (fref) = 486 → 1E6 (HEX)
DVS
SNS
Input pin
Set divisor
Actual divisor: N
Input frequency range (MHz)
A
1
*
FMIN
272 to 65535
Twice the set value
10 to 160
B
0
1
AMIN
272 to 65535
The set value
2 to 40
C
0
AMIN
4 to 4095
The set value
0.5 to 10
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