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參數(shù)資料
| 型號： | LC72146V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LC72146V |
The unlock detection data UL1 must be set to 1. The unlock detection range will be set to ±0.56 s or ±1.11 s. If a
phase difference in excess of these values is detected the circuit will go to the unlock state and the sub-charge pump will
operate. When the circuit approaches the lock state and the phase difference falls under the unlock detection range, the
sub-charge pump operation will stop, i.e., the sub-charge pump will go to the high impedance state.
Note: 1. Notes on the phase comparator dead zone
Cases where the charge pump is in the ON/ON state require special care during system design since the charge
pump outputs correction pulses even when the PLL is locked and it is easy for the loop to become unstable.
The following problems may occur in the ON/ON state.
x Sidebands may be generated by reference frequency leakage.
y Sidebands may be generated by low frequency leakage due to the correction pulse envelope.
The settings that have a dead zone (the OFF/OFF settings) provide good loop stability, but it is hard to achieve
a good S/N ratio with these settings. Inversely, the settings with no dead zone (the ON/ON settings) allow a
high S/N ratio to be achieved but it is hard to achieve good loop stability with these settings.
Therefore, it can be effective to select either the DZA or DXB setting, i.e., a setting which has no dead zone,
when an S/N ratio of between 90 and 100 dB or higher is required in FM mode, or when the AM stereo pilot
margin needs to be increased. However, in cases where such a high FM S/N ratio is not required and where an
adequate AM stereo pilot margin can be achieved or AM stereo is not used, either the DZC or DZD setting,
i.e., a setting which has a dead zone, should be selected.
Dead Zone Definition
The phase comparator compares fp with a reference frequency (fr) as shown in Figure 11. Figure 12 shows the
characteristics of an ideal phase comparator, which outputs an output voltage (A) that is proportional to the
phase difference . However, in an actual IC, a region (dead zone) in which minute phase differences cannot
be detected occurs due to internal circuit delays and other factors. To implement an end product with a high
S/N ration, the dead zone should be as small as possible.
However, there are cases where a larger dead zone can make a popularly-priced model easier to use. This is
because it is possible for RF leakage from the mixer to the VCO to modulate the VCO in popularly-priced
models when a strong RF input is applied. When the dead zone is small an output that compensates for this
problem is generated, and this output may itself modulate the VCO and generate beating with the RF
frequency.
No. 4922-18/22
LC72146, 72146M, 72146V
DZ1
DZ0
Dead zone mode
Charge pump
Dead zone
0
DZA
ON/ON
– –0 s
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
DZD
OFF/OFF
+ +0 s
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72147V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems |
| LC72148V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Electronic Tuning PLL Frequency Synthesizer for Car Stereo Systems |
| LC72148V-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack 制造商:ON Semiconductor 功能描述:Phase Locked Loops - PLL |
| LC72148V-TLM-E | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC7215 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
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