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參數(shù)資料
| 型號： | LC72146V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LC72146V |
1. Serial data input (IN1/IN2)
2. Serial data output (OUT)
Note: 1. The data conversion time varies with the value of the pull-up resistor, since the DO pin is an n-channel open drain circuit.
2. The DO pin is normally open.
Programmable Divider
The configuration of the programmable divider is shown in Figure 7. The input mode selection is shown in Table 14, and
the input sensitivity, in Table 15.
Figure 7 Programmable Divider
Table 14 Programmable Divider Selection
Note:
× = don’t care
No. 4922-14/22
LC72146, 72146M, 72146V
DVS
SNS
Divisor setting (NO)
Input frequency range
Input port
1
×
272 to 65535
10 to 160 MHz
FMIN
0
1
272 to 65535
2 to 40 MHz
AMIN
0
4 to 4095
0.5 to 10 MHz
AMIN
tSU
tHD
tEL
tDC
tES
tCL
tDH
tCH
tSU tHD tEL tES tEH tCL tCH > 0.45 S
tDC tDH < 0.2 S (*1)
B0
B1
B2
B3
A0
A1
A2
A3
I7
I6
I5
I4
C3
C2
C1
C0
CE
CL
DI
DO
(*2)
tEH
fvco/N
fref
fvco=fref x N
PD
E
12bits
4bits
FMIN
AMIN
(C)
(A)
(B)
Swallow
Counter
Programmable
Divider
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
CTS0 CTS1 GT0
GT1
CE
tSU
tHD
tEL
tES
tCL
tCH
tEH
tLC
tSU tHD tEL tES tEH tCL tCH > 0.45 S
tLC < 0.45 S
CL
DI
Internal data
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| LC72147V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems |
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| LC7215 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
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