參數(shù)資料
型號： LC72147V
廠商： Sanyo Electric Co.,Ltd.
英文描述： PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems
中文描述： 鎖相環(huán)頻率合成器在汽車音響系統(tǒng)的電子調(diào)諧
文件頁數(shù)： 3/22頁
文件大?。?/td> 154K
代理商： LC72147V
No. 6675-3/22
LC72147V
Parameter
Symbol
Pin
Conditions
Ratings
Unit
Supply voltage
V
DD
max
V
IN
1 max
V
IN
2 max
V
IN
3 max
V
O
1 max
V
O
2 max
V
O
3 max
I
O
1 max
I
O
2 max
I
O
3 max
I
O
4 max
I
O
5 max
Pd max
V
DD
CE, CL, DI, AIN
–0.3 to +7.0
V
–0.3 to +7.0
Maximum input voltage
XIN, FMIN, HCTR, I/O-4, I/O-5, ADC0, ADC1
–0.3 to Vreg + 0.3
V
I/O-1 to I/O-3
–0.3 to +15
DO
–0.3 to +7.0
Maximum output voltage
XOUT, IFBC, I/O-4, I/O-5, PD, XBUF
–0.3 to Vreg + 0.3
V
I/O-1 to I/O-3, AOUT
–0.3 to +15
IFBC
0 to 1.0
I/O-4, I/O-5, XBUF
0 to 3.0
Maximum output current
DO
0 to 6.0
mA
I/O-1 to I/O-3
0 to 10
AOUT
0 to 35
Allowable power dissipation
Ta
≤
85°C
150
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Note: Power supply V
DD
- V
SS
, Vreg - V
SS
: Capacitors of at least 2000 pF must be inserted between these pins when this device is used.
Allowable Operating Ranges
at Ta = –40 to 85°C, V
SS
= 0 V
Parameter
Symbol
Pin
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
2
Vreg
V
DD
V
DD
Vreg
4.5
6.5
V
Serial data retention voltage
4.5
≤
V
DD
≤
6.5 V
2.5
Regulator output voltage
2.7
3.0
3.3
V
V
IH
1
CE, CL, DI,
I/O-1 to I/O-3
2.2
6.5
V
High-level input voltage
V
IH
2
I/O-4, I/O-5
2.2
Vreg
Low-level input voltage
V
IL
CE, CL, DI,
I/O-1 to I/O-5
0
0.8
V
Output voltage
V
O
1
V
O
2
f
IN
1
f
IN
2
f
IN
3
X’tal1
DO
0
6.5
V
I/O-1 to I/O-3
0
13
XIN
Sine wave, capacitance coupled
1.0
8.0
Input frequency
FMIN
Sine wave, capacitance coupled
10
180
MHz
HCTR
Sine wave, capacitance coupled
0.4
25
Guaranteed crystal oscillator
frequency ranges
XIN, XOUT
*
1
4.0
7.0
MHz
X’tal2
XIN, XOUT
*
1
7.1
10.5
V
IN
1
V
IN
2-1
V
IN
2-2
V
IN
3-1
V
IN
3-2
V
IN
4
t
SU
t
HD
t
CL
t
CH
t
EL
t
ES
t
EH
t
LC
t
DC
t
DH
XIN
200
900
FMIN
10
≤
f < 130 MHz
*
2
130
≤
f
≤
180 MHz
*
2
0.4
≤
f
≤
25 MHz
*
3
8
≤
f
≤
12 MHz
*
4
40
900
Input amplitude
FMIN
70
900
mVrms
HCTR
70
900
HCTR
100
900
Input voltage range
ADC0, ADC1
0
Vreg
V
Data setup time
DI, CL
*
5
0.45
μs
Data hold time
DI, CL
*
5
0.45
μs
Clock low-level period
CL
*
5
0.45
μs
Clock high-level period
CL
*
5
0.45
μs
CE wait time
CE, CL
*
5
0.45
μs
CE setup time
CE, CL
*
5
0.45
μs
CE hold time
CE, CL
*
5
0.45
μs
Data latch change time
*
5
0.45
μs
Data output time
DO, CL
Depends on the value of the pull-up
resistor used.
0.2
μs
DO, CE
Notes:1. Recommended crystal oscillator CI values
CI
≤
120
(Crystal: 4.5 MHz), CI
≤
70
(Crystal: 7.2, 10.25, or 10.35 MHz)
Note that the crystal oscillator circuit characteristics depend on the printed circuit board and the particular components used. We recommend
consulting the manufacturer of the crystal when designing this circuit.
2. Refer to the description of the structure of the programmable divider.
3. Serial data: CTC = 0
4. Serial data: CTC = 1
5. See the timing chart for serial data transfers.
相關(guān)PDF資料
PDF描述
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