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參數(shù)資料
| 型號： | LC72148V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 170K |
| 代理商： | LC72148V |
Structure of the DO output data (serial output data)
[3] OUT mode
No. 6974-13/21
LC72148V
DI
0
1
0
1
0
1
0
DO
I7
I6
I5
I4
I3
I2
I1
*
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
*
(1)
IN-PORT
(2)
IF-CTR
*: Must be set to 0.
Address
Description of the DO output data
Number
Control block/data
Description
Related data
This data is latched from the states of I/O port pins I-1 to I-7.
This data outputs (reports) the states of the pins regardless of the I/O direction specified for the
I/O ports. Data is latched at the point data output mode (OUT mode) is entered.
I1 to I5
← The I/O-1 to I/O-5 pin states
Hi : “1”
I6, I7
← The HCTR/I-6 and LCTR/I-7 pin states
Low : “0”
The following data is output if these pins are set to function as output ports or as general-
purpose counter input pins.
I1, I2, I3: Output pin states (open drain)
I4, I5: Output pin state (CMOS)
I6, I7: 0
I/O-1 to I/O-5
H/I-6, L/I-7
OUT1 to OUT5
(1)
I/O port data
I7 to I1
This data is latched from the contents of the IF counter (the 20-bit binary counter).
C19
← MSB of the binary counter
C0
← LSB of the binary counter
CTE
CTS0
CTS1
(2)
IF counter binary data
C19 to C0
Serial data input (IN1/IN2)
tSU, tHD, tEL, tES, tEH ≥ 0.45 s tLC < 0.45 s
CE
CL
DI
Internal data
tHD
tSU
tES
tEL
tEH
tLC
B0
B1
B2
B3
A0
A1
A2
P0
P1
P2
P3
CTS0 CTS1
GT0
GT1
A3
CE
CL
DI
DO
Note: Since the DO pin is an n-channel open-drain output, the data output times (tDC and tDH)
depend on the value of the pull-up resistor used and the circuit board capacitance.
tHD
tSU
tES
tEL
tDC
tEH
tDH
B0
B1
B2
B3
A0
A1
A2
I7
I6
I5
I4
C3
C2
C1
C0
A3
Serial data output (OUT)
tSU, tHD, tEL, tES, tEH ≥ 0.45 s tDC, tDH < 0.2 s
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