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參數(shù)資料
| 型號(hào)： | LC72720YV |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 107K |
| 代理商： | LC72720YV |
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No. 6488-10/14
LC72720Y, 72720YV
Caution: The output indicates the synchronization state for the previous block.
Mode (PT2 = 0)
The SYNC pin
0 to 2
When synchronized: Low (0). When unsynchronized: High (1)
When synchronized: Goes high for a fixed period (421 s) at
3
the start of a block and then goes low.
When unsynchronized: High (1)
When PT2 = 0
The RDS-ID pin
No RDS
High (1)
RDS present
Low (0)
(10) Test mode settings (4 bits): TS0 to TS3
Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above values.)
Notes: The T1 and T2 pins (pins 7 and 8) are related to test mode as follows:
The T1 pin must be tied to VSS (0 V).
Initial values: CT0 = 0, CT1 = 0
Pin T1
Pin T2
IC operation
Notes
0
Normal operating mode
These states are user settable
0
1
Standby mode (crystal oscillator stopped)
1
0/1
IC test mode
Users cannot use this state
(11) Circuit control (2 bits): CT0 and CT1
RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing
Timing 1 (modes 1 to 3, PT2 = 0)
Timing 2 (mode 3, PT2 = 0)
Item
Control
CT0
RSFT control
When set to 1, soft-decision control data (RSFT) is easier to generate.
CT1
RDS-ID detection condition
When set to 1, the RDS-ID detection conditions are made more restrictive.
Tp1
421
s
421
s
842
s
421
s
A13210
A13211
Tp1
RDCL output
RDDA output
RSFT output
Input data
Error crrection
SYNC output
ERROR output
CORREC output
Sync NG
Sync OK
Data
corrected
Data
corrected
No
errors
No
errors
Uncorrectable
Note: When PT2 = 0, RDDA and RSFT must be
aquired on the falling edge of RDCL.
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| LC72720YVS | 制造商:SANYO 制造商全稱(chēng):Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System IC |
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