參數(shù)資料
型號: LC74401E
元件分類: 畫面疊加
英文描述: PICTURE-IN-PICTURE IC, PQFP80
封裝: QFP-80
文件頁數(shù): 8/19頁
文件大?。?/td> 352K
代理商: LC74401E
Initialization
1. RES pin: Reset
The RES pin must be set low when power is first applied.
2. Internal control registers
These LSIs go to the standby state (SBY = high) after a reset. When developing microprocessor software, be sure to
send data to all registers. Also be sure to send zero data to the zero registers at addresses 14H and 15H.
I2C Control
Data format
Data 1 is stored at register address A1. For data 2, A1 is incremented and data 2 is stored at A1 + 1.
Slave Address
Synchronization Signal Input
1. Sync separator
The LC74401E requires sync separated (including AFC processing) V and H signals for both the main and sub-
screens. Since V is used for frame determination and H is used as the PLL reference signal, these signals must be
input reliably.
The standard values are set up assuming that the H-M and H-S inputs are delayed about 1 s from the video signal
horizontal synchronization signal.
Equalizing pulses must be removed.
Since noise in the synchronization signal will disrupt the screen image, care must be used in the layout of these lines.
We recommend turning off sub-screen display when the synchronization signals are unstable, since such instability
can disrupt the sub-screen image.
No. 4872-16/19
LC74401E, 74402, 74402E
A6
A5
A4
A3
A2
A1
A0
R/W
0
1
0
1
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