參數(shù)資料
型號: LC74401E
元件分類: 畫面疊加
英文描述: PICTURE-IN-PICTURE IC, PQFP80
封裝: QFP-80
文件頁數(shù): 9/19頁
文件大?。?/td> 352K
代理商: LC74401E
2. Field determination circuit
Since the field is determined by the phase difference between the falling edges of the V and H signals, these signals
must be input with the timing shown in the figure.
Here, a and b must be: a = 0.02 to 0.40 H, b = 0.60 to 0.98 H.
The synchronization signal pulse widths are: tWV > 1 s, tWH > 1 s.
Clamping Pulses
1. A/D converter clamping
Since clamping pulses are output with the timing shown in the figure, they must set to fall in the pedestal range. On a
reset or during standby mode, the H-S input signal becomes a positive polarity signal, and is output as such.
Note: Here, t3 and t4 must be: t3 > 0 s, t4 > 0.5 s.
2. D/A converter clamping
The digital data for the regions A is as follows:
Y D/A converter input:
000000
R-Y D/A converter input: 100000
B-Y D/A converter input: 100000
Clamping is applied on the main screen horizontal synchronization signal.
No. 4872-17/19
LC74401E, 74402, 74402E
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