參數(shù)資料
型號(hào): LC74794
廠商: Sanyo Electric Co.,Ltd.
英文描述: On-Screen Display Controller LSI(用于屏幕顯示控制器規(guī)模集成電路(LSI))
中文描述: 屏幕顯示控制器芯片(用于屏幕顯示控制器規(guī)模集成電路(LSI)的)
文件頁(yè)數(shù): 3/30頁(yè)
文件大?。?/td> 217K
代理商: LC74794
No. 5557-3/30
LC74794, 74794M
Continued from preceding page.
Pin no.
Pin
Function
Notes
Enable input for OSD serial data input
Serial data input is enabled by a low-level input.
(A pull-up resistor is built in so the input has hysteresis characteristics.)
9
CS1
Enable input 1
10
SCLK1
Clock input 1
Serial data clock input
(A pull-up resistor is built in so the input has hysteresis characteristics.)
11
SIN1
Data input 1
Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.)
12
V
DD
2
CP
OUT
VCO
IN
V
SS
3
V
DD
3
VCO
R
DAV
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
Charge pump output
The charge pump output. Connect a low-pass filter to this pin.
14
Oscillator control voltage input
VCO control voltage input
15
Ground
Ground (VCO ground)
16
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
17
Oscillator range adjustment
Connection for the VCO range adjustment resistor
18
Data present output
Outputs a low level when PDC/VPS data has been received.
19
CV
OUT
V
SS
2
CV
IN
CV
CR
V
DD
1
SYN
IN
SEPC
Video signal output
Composite video signal output
20
Ground
Ground (analog system ground)
21
Video signal input
Composite video signal input
22
Video signal input
SECAM chrominance signal input
23
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
Sync separator circuit input
Internal sync separator circuit video signal input
25
Sync separator circuit adjustment
Internal sync separator circuit adjustment input
Composite synchronizing signal output for the built-in sync separator circuit. Can be
switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting
SEL0 high.
26
SEP
OUT
Composite synchronizing signal output
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output
signal.
An integration circuit must be connected to the SEP
OUT
pin. This pin must be tied to V
DD
1
if unused.
27
SEP
IN
Vertical synchronizing signal input
28
CDLR
Background color phase adjustment
Background color phase adjustment resistor connection
29
RST
Reset input
System reset input
A pull-up resistor is built in so the input has hysteresis characteristics.
30
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
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