參數(shù)資料
型號(hào): LC749460W
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP256
封裝: 28 X 28 MM, LQFP-256
文件頁(yè)數(shù): 8/20頁(yè)
文件大小: 140K
代理商: LC749460W
LC749460W
No.A1187-16/20
A/D Convertor Characteristics at Ta = -30 to +70
°C, DVSS = 0V, AVSS = 0V
Electric characteristic
Parameter
Symbol
Conditions
min
typ
max
unit
Sampling frequency
FCLK
10
80
MHz
Clamp pulse width
Tcl
0.45
μs
Analog input coupling capacitor
Cal
0.1
μF
Analog input frequency
Fal
30
MHz
Analog input amplitude
Val
1.0
Vp-p
SVO amplifier bandwidth
FSVO
5MHz
SVO amplifier output load capacitor
CSVO
20
pF
External between DACREFP/DACREFM capacitor
CEXT
0.08
0.1
1
μF
ADC Characteristics
Parameter
Symbol
Conditions
min
typ
max
Unit
resolution
NOB
10
bits
*1
8
bits
ENOB
*2
7.5
bits
*1
0.5
LSB
Derivative linearity error
DNL
*2
0.5
LSB
*1
2
LSB
Integral linearity error
INL
*2
2
LSB
Operation power current
3.3V power
IDD3
*2, *3
60
mA
1.2V power
IDD
*2, *3
1.5
mA
Standby power current
3.3V power
ISB3
*3
-10
+10
μA
1.2V power
ISB
*3
-10
+10
μA
*1 VDD3=3.3V, Fclk=27MHz, Fin=100KHz
*2 VDD3=3.3V, Fclk=80MHz, Fin=100KHz
*3 It describes value per 1ch
Note: ADC cannot standby. Apply a square wave with a constant frequency when ADC is not to be used.
I/O Data Timing
(1) Input data timing 1
Pin name
Parameter
Symbol
min
max
Unit
Clock L-level time
tLO
6.25
ns
Clock H-level time
tHI
6.25
ns
CK1I, CK2I
Clock cycle
tCK
12.5
ns
Input data setup time
tSU
2
ns
YGI [7:0], CBI [7:0], CRI [7:0],
HE1I, VE1I, HS1I, VS1I,
FLD1I, HS2I, VS2I, FLD2I
Input data hold time
tHD
1
ns
* The recommended duty cycle of input clock is 50%
tHI
tLO
tCK
tSU
tHD
CLK
Input data
VDD33/2
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