參數(shù)資料
型號(hào)： LC74950BG
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 6 X 6 MM, FBGA-96
文件頁(yè)數(shù)： 11/37頁(yè)
文件大?。?/td> 350K
代理商： LC74950BG
LC74950BG
No.A1647-19/37
2) SYNC width adjustment (H-lock PLL mode only) of horizontal sync output (HSOUT)
Registers related to SYNC width adjustment of HSOUT
Name
Functions
Sub address
bit width
HSPLLSEL
This register selects the horizontal sync signal (SHOUT) in the H-lock PLL mode.
0: HSIN
1: This is the signal that is fed back to the phase detector after dividing the VCO output
of the PLL.
*: SYNC width adjustment for HSOUT must be turned on when HSPLLSEL is set to 1.
0x01
1
CORREN
This register turns on and off the SYNC width adjustment for HSOUT.
0: OFF, 1: ON
0x27
1
CORRHSS
SYNC width adjustment register for HSOUT (to be described below)
0x2B
0x2C
12
CORRHSE
SYNC width adjustment register for HSOUT (to be described below)
0x2B
0x2D
12
When "1" is set for HSPLLSEL in the H lock PLL mode, the horizontal sync output signal is not HSIN but the signal
that is fed back to the phase detector after dividing the VCO output of the PLL. The duty ratio of this signal is 50%,
which means when it is to be used as the horizontal sync signal, the sync width must be determined. Furthermore, if "0"
is set for HSPLLSEL, the horizontal sync input (HSIN) signal can be output in its original form even in the H lock PLL
mode.
*1: Clock is expressed in units of CLKOUT1.
*2: A value equivalent to about three-fourths of one HSOUT period (640 or so with the NTSC system) must be set as
the CORRHSE[11:0] value.
(CORRHSS [11:0] + 3) clock *1
CORRHSE [11:0] *2
HSOUT
(HSOUTINV=0)
Feedback signal to the
phase detector
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參數(shù)描述
LC74950BG-TLM-H 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
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