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參數(shù)資料
| 型號： | LC74950BG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 6 X 6 MM, FBGA-96 |
| 文件頁數(shù)： | 7/37頁 |
| 文件大小： | 350K |
| 代理商： | LC74950BG |
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LC74950BG
No.A1647-15/37
Registers related to the control of clock
Name
Functions
Sub address
bit width
CLKININV
This register controls the inversion of CLKIN when the CLKIN input is used as a
reference clock to PLL.
0: Uses CLKIN in its original form
1: Uses CLKIN in its inverted form
0x00
2
HSINV
This register controls the inversion of HSIN input. The HSIN must be used in its
inverted form when the polarity of HSIN input is negative.
0: Original form (when HSIN is positive)
1: Inverted form (when HSIN is negative)
0x02
1
CLKINDIV
This register sets the frequency division ratio of CLKIN to an arbitrary value
(1/1 to1/64) when the CLKIN is used as a reference clock to PLL.
1/(CLKINDIV[5:0]+1) division
0x40
6
CLKSEL
This register selects the operating mode.
000: (External clock mode (PLL not used)
001: (External clock mode (PLL used)
010: H-lock PLL mode
011: Panel PLL mode <1>
100: Panel PLL mode <2>
0x00
3
CLKADCINV
This register controls the inversion of the ADC sampling clock (CLKADC).
0: Uses CLKADC in its original form
1: Uses CLKADC in its inverted form
0x00
1
CLKOUTINV
This register controls the inversion of the ADC-generated clock. (CLKOUT).
0: Uses CLKOUT in its original form
1: Uses CLKOUT in its inverted form
0x01
1
CLKOUT1INV
This register controls the inversion of CLKOUT (video clock output).
0: Original form
1: Inverted form
0x00
1
CLKOUT2INV
This register controls the inversion of CLKOUT2 (panel clock output).
0: Original form
1: Inverted form
0x00
1
*2 Clock control register (CLKSEL, 00h, bits 2-0) specifications
CLKSEL
(bit2-0)
CLKADC*3
(ADC sampling clock)
FIN
(PLL reference)
CLKOUT2
(Clock output)
Remarks
000
CLKIN/2 (13.5MHz)
L fixed (PLL not used)
CLKIN(27MHz)
External clock mode (PLL not used)
001
FOUT (PLL output)
CLKIN *4
FOUTX2
(PLL output X2)
External clock mode (PLL used)
010
FOUT (PLL output)
HSIN *5
FOUTX2
(PLL output X2)
H-lock PLL mode
011
CLKIN/2
CLKIN *4
FOUT (PLL output)
Panel PLL mode <1>
100
CLKIN
CLKIN *4
FOUT (PLL output)
Panel PLL mode <2>
*3: Register CLKADCINV (00h, bit 3) allows for clock inversion.
*4: Register CLKINDIV (40h, bits 5-0) allows for division of clock frequency (1/1 to 1/64).
*5: Register HSINV (03h, bit 3) allows for HSIN inversion.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LC74950BG-TLM-H | 功能描述:視頻模擬/數(shù)字化轉換器集成電路 RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| LC74980W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC74981W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC74982W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:LCD TV Scan Converter IC |
| LC749870W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Silicon gate NTSC/PAL/SECAM Digital Video Decoder |
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