參數(shù)資料
型號: LC75817NW
廠商: Sanyo Electric Co.,Ltd.
英文描述: 1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function
中文描述: 1月8日至1月10日當(dāng)值點陣液晶顯示控制器/輸入功能的關(guān)鍵驅(qū)動
文件頁數(shù): 4/43頁
文件大?。?/td> 829K
代理商: LC75817NW
No. 6144-4/43
LC75817E, 75817W
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
LCD
max
V
IN
1
V
IN
2
V
IN
3
V
OUT
1
V
OUT
2
V
OUT
3
I
OUT
1
I
OUT
2
I
OUT
3
I
OUT
4
Pd max
V
DD
V
LCD
CE, CL, DI, INH
–0.3 to +7.0
V
–0.3 to +11.0
V
–0.3 to +7.0
V
Input voltage
OSCI, KI1 to KI5, TEST
–0.3 to V
DD
+ 0.3
–0.3 to V
LCD
+ 0.3
–0.3 to +7.0
V
V
LCD
1, V
LCD
2, V
LCD
3, V
LCD
4
DO
V
V
Output voltage
OSCO, KS1 to KS6, P1 to P4
–0.3 to V
DD
+ 0.3
–0.3 to V
LCD
+ 0.3
V
V
LCD
0, S1 to S60, COM1 to COM10
S1 to S60
V
300
μA
Output current
COM1 to COM10
3
mA
KS1 to KS6
1
mA
P1 to P4
5
mA
Allowable power dissipation
Ta = 85°C
200
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
DD
V
DD
When the display contrast adjustment circuit is used.
4.5
6.0
V
Supply voltage
V
LCD
7.0
10.0
V
When the display contrast adjustment circuit is not used.
4.5
10.0
V
Output voltage
V
LCD
0
V
LCD
1
V
LCD
2
V
LCD
3
V
LCD
4
V
IH
1
V
IH
2
V
IH
3
V
IL
1
V
IL
2
R
OSC
C
OSC
f
OSC
t
ds
t
dh
t
cp
t
cs
t
ch
tH
V
LCD
0
V
LCD
1
V
LCD
2
V
LCD
3
V
LCD
4
CE, CL, DI, INH
V
LCD
4+4.5
V
LCD
V
LCD
0
V
LCD
0
V
LCD
0
V
3/4 (V
LCD
0
V
LCD
4)
2/4 (V
LCD
0
V
LCD
4)
1/4 (V
LCD
0
V
LCD
4)
V
Input voltage
V
V
0
1.5
V
0.8 V
DD
0.7 V
DD
0.6 V
DD
6.0
V
Input high level voltage
OSCI
V
DD
V
DD
V
KI1 to KI5
V
Input low level voltage
CE, CL, DI, INH, KI1 to KI5
0
0.2 V
DD
0.3 V
DD
V
OSCI
0
V
k
pF
Recommended external resistance
OSCI, OSCO
33
Recommended external capacitance
OSCI, OSCO
220
Guaranteed oscillation range
OSC
150
300
600
kHz
Data setup time
CL, DI: Figure 2
160
ns
Data hold time
CL, DI: Figure 2
160
ns
CE wait time
CE, CL: Figure 2
160
ns
CE setup time
CE, CL: Figure 2
160
ns
CE hold time
CE, CL: Figure 2
160
ns
High level clock pulse width
CL: Figure 2
160
ns
Low level clock pulse width
tL
CL: Figure 2
DO, R
PU
= 4.7k
, C
L
= 10pF: Figure 2
*
1
DO, R
PU
= 4.7k
, C
L
= 10pF: Figure 2
*
1
160
ns
DO output delay time
t
dc
t
dr
1.5
μs
DO rise time
1.5
μs
Allowable Operating Ranges
at Ta = –40 to +85°C, V
SS
= 0 V
Note:
*
1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor R
PU
and the load capacitance C
L
.
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