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參數(shù)資料
| 型號： | LC7872E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 295K |
| 代理商： | LC7872E |
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Allowable Operating Ranges at Ta = 25°C, VSS = 0 V
Electrical Characteristics at Ta = 25°C, VSS = 0 V, VDD = 5 V
No. 4868-3/17
LC7872E
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD max
VSS – 0.3 to +7.0
V
Maximum input voltage
VIN max
VSS – 0.3 to VDD + 0.3
V
Maximum output voltage
VOUT max
VSS – 0.3 to VDD + 0.3
V
Allowable power dissipation
Pd max
300
mW
Operating temperature
Topr
–30 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
VDD
VDD1, VDD2
4.5
5.5
V
VIH (1)
RESET
0.7 VDD
VDD
V
Input high level voltage
VIH (2)
SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3,
2.2
VDD
V
PALID, HRESET, VRESET, N/P1, N/P2, SON
VIH (3)
S1, S2, CB, TEST, TEST1, LINE, DEN
0.8 VDD
VDD
V
VIL (1)
RESET
VSS
0.3 VDD
V
Input low level voltage
VIL (2)
SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3,
VSS
0.8
V
PALID, HRESET, VRESET, N/P1, N/P2, SON
VIL (3)
S1, S2, CB, TEST, TEST1, LINE, DEN
VSS
0.2 VDD
V
High level clock pulse width
tH
CL: Figure 1
400
ns
Low level clock pulse width
tL
CL: Figure 1
400
ns
Data setup time
tDS
CL, DI: Figure 1
200
ns
Data hold time
tDH
CL, DI: Figure 1
200
ns
CE wait time
tCP
CE, CL: Figure 1
400
ns
CE setup time
tCS
CE, CL: Figure 1
400
ns
CE hold time
tCH
CE, CL: Figure 1
400
ns
DO setup time
tDOS
CL, DO: Figure 1
130
300
ns
fin (1)
XIN1
14.31818
MHz
fin (2)
XIN2
17.734476
MHz
Input frequency
fin (3)
4FSC2
NTSC mode
14.31818
MHz
PAL mode
17.734476
MHz
fin (4)
FSCIN
NTSC mode
3.58
MHz
PAL mode
4.43
MHz
Input amplitude
VIN
XIN1, XIN2, 4FSC2, FSCIN:
0.3
5
Vp-p
sine wave, capacitive coupling
Reset pulse width
tWRES
RESET
400
ns
Parameter
Symbol
Conditions
min
typ
max
Unit
Current drain
IDD (1)
VDD124
40
mA
IDD (2)
VDD212
20
mA
S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE,
Input high level current
IIH (1)
HRESET, VRESET, N/P1, N/P2, RESET, SON:
5
A
VIN = VDD
IIH (2)
CB, TEST, TEST1, DEN: VIN = VDD
30
100
200
A
S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE,
Input low level current
VIL (1)
HRESET, VRESET, N/P1, N/P2, RESET, SON:
–5
A
VIN = VSS
VIL (2)
PALID: VIN = VSS
–200
–100
–30
A
SBCK, WE, RAS, CAS, OE, A0 to A7, DB0 to DB3,
Output high level voltage
VOH
CDGM, TRANS0 to TRANS5, VSYNC, YS, CSYNC,
VDD – 1
VDD
V
EFLG, FSX, FSC: IO = –0.5 mA
Continued on next page.
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