參數(shù)資料
型號: LC868008A
廠商: Sanyo Electric Co.,Ltd.
英文描述: 8-Bit Single Chip Microcontroller with On-Chip 8K(8192 ×8 bits)-Byte ROM and 640(640 ×8 bits)-Byte RAM(8位單片微控制器(帶片上8K(8192 ×8 bits)字節(jié)ROM和640(640 ×8 bits)字節(jié)RAM))
中文描述: 8位單片機(jī)微控制器的片上8K的(8192 × 8位)字節(jié)ROM和640(640 × 8位)字節(jié)的RAM(8位單片微控制器(帶片上8K的(8192 × 8位)字光盤和640節(jié)(640 × 8位)字節(jié)的RAM))
文件頁數(shù): 26/28頁
文件大?。?/td> 689K
代理商: LC868008A
LC868016/12/08A
26/28
External data memory timing
Ratings
Parameter
Symbol
Pads and Conditions
VDD[V]
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
min.
max.
unit
6tCLCL-80
6tCLCL-320
6tCLCL-80
6tCLCL-320
2tCLCL-35
2tCLCL-140
2tCLCL-35
2tCLCL-140
0
0
2tCLCL-70
2tCLCL-280
tCLCL-40
tCLCL-160
3tCLCL-50
3tCLCL-200
3tCLCL-50
3tCLCL-200
tCLCL-60
tCLCL-240
7tCLCL-140
7tCLCL-560
tCLCL-50
tCLCL-200
tCLCL-50
tCLCL-200
tCLCL-50
tCLCL-200
RD
pulse width
tRLRH
WR
pulse width
tWLWH
For ADLC (at LDX)
Data address hold time
tLLAX
For ADLC (at STX)
5tCLCL-125
5tCLCL-400
2tCLCL+70
2tCLCL+280
3tCLCL+50
3tCLCL+200
3tCLCL+50
3tCLCL+200
tCLCL+50
tCLCL+200
tCLCL+50
tCLCL+200
Data delay time
tRLDV
From
RD
Data hold time
tRHDX
From RD
Data floating time
tRHDZ
From RD
Data address setting
time
ADLC
!
control signal
tAVLL
For ADLC
tLLRL
For
RD
tLLWL
For
WR
Data settling time
tQVWL
For
WR
Data in
WR
=1
tQVWH
Data hold time
tWHQX
From
WR
tRHLH
For RD
Control signal
!
ADLC
tWHLH
For
WR
ns
Refer to figure 14.
SCLK
tCLCL
1 tCYC
EROE
ADLC
RD
WR
Port 0
Port 0
Port 2
Port 3
Port 5
tRLRH
tRHLH
tRLDV
tAVLL
tLLAX
(at reading)
tRHDX
tRHDZ
A7-A0
tLLWL
tWLWH
tWHLH
tLLRL
tLLAX
(at writing)
tQVWL
tWHQX
DATA
Z
A7-A0
DATA
tQVWH
A15-A8
Bank
A7-A0
Figure 14 Timing of the external RAM
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