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參數(shù)資料
| 型號(hào)： | LC877280B |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 662K |
| 代理商： | LC877280B |
LC8772C8B/B2B/96B/80B
No.6842-12/24
2. Recommended Operating Range at Ta=-30
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD
[V]
min.
4.5
max.
6.0
unit
VDD(1)
0.294
μ
s
≤
t
CYC
≤
200
μ
s
0.735
μ
s
≤
t
CYC
≤
200
μ
s
Keep RAM and
register data in
HOLD mode.
Output disable
Operating
supply voltage
range
VDD(2)
VDD1=VDD2=VDD3
2.5
6.0
Supply voltage
range in Hold
mode
Input high
voltage
VHD
VDD1
2.0
6.0
VIH(1)
Port 0, 3, 8
Port A,B,C,D,E,F,L
Port 1
Port 71,72,73
P70 port input/interrupt
P87 small signal input
Port 70
Watchdog timer
2.5 to 6.0 0.3VDD
+0.7
VDD
VDD
VIH(2)
Output disable
2.5 to 6.0 0.3VDD
+0.7
VIH(3)
VIH(4)
Output disable
Output disable
2.5 to 6.0 0.75VDD
2.5 to 6.0 0.9VDD
VDD
VDD
VIH(5)
VIL(1)
XT1, XT2, CF1,
RES
Port 0, 3, 8
Port A,B,C,D,E,F,L
Port 1
Port 71,72,73
P70 port input/interrupt
Port 87 small signal input Output disable
Port 70
Watchdog timer
XT1,XT2,CF1,
RES
Output disable
2.5 to 6.0 0.75VDD
2.5 to 6.0
VDD
0.15VDD
+0.4
0.1VDD
+0.4
VSS
VIL(2)
Output disable
2.5 to 6.0
VSS
VIL(3)
VIL(4)
2.5 to 6.0
2.5 to 6.0
VSS
VSS
0.25VDD
0.8VDD
-1.0
0.25VDD
200
Output disable
Input low
voltage
VIL(5)
t
CYC
2.5 to 6.0
4.5 to 6.0
VSS
0.294
V
Operation
cycle time
2.5 to 6.0
4.5 to 6.0
0.735
0.1
200
10
μ
s
CF2 open
system clock
divider :1/1
external clock
DUTY = 50±5%
2.5 to 6.0
0.1
4
4.5 to 6.0
0.2
20
External system
clock
frequency
FEXCF(1) CF1
CF2 open
system clock
divider :1/2
2.5 to 6.0
0.2
8
Continued/
MHz
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