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參數(shù)資料
| 型號(hào)： | LC877296B |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 662K |
| 代理商： | LC877296B |
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LC8772C8B/B2B/96B/80B
No.6842-8/24
Pin Assignment
Pin name
VSS1
VSS2
VSS3
VDD1
VDD2
VDD3
PORT0
P00 to P07
I/O
-
Function
Option
No
Power supply (-)
-
Power supply (+)
No
I/O
8bit input/output port
Data direction programmable in nibble units
Use of pull-up resistor can be specified in nibble units
Input for HOLD release
Input for port 0 interrupt
8bit input/output port
Data direction programmable for each bit
Use of pull-up resistor can be specified for each bit individually
Other pin functions
P10 SIO0 data output
P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
6bit Input/output port
Data direction can be specified for each bit
Use of pull-up resistor can be specified for each bit individually
4bit Input/output port
Data direction can be specified for each bit
Use of pull-up resistor can be specified for each bit individually
Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog
timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input
P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture
input
AD input port: AN8(P70), AN9(P71)
Interrupt detection selection
Yes
PORT1
P10 to P17
I/O
Yes
PORT3
P30 to P35
I/O
Yes
Rising
Falling
Rising and
falling
No
No
Yes
Yes
H level
L level
INT0
INT1
INT2
INT3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
PORT7
P70 to P73
I/O
No
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