參數(shù)資料
型號(hào): LC8905V
廠商: Sanyo Electric Co.,Ltd.
英文描述: Digital Audio Interface Receiver(數(shù)字音頻接口接收器)
中文描述: 數(shù)字音頻接口接收器(數(shù)字音頻接口接收器)
文件頁數(shù): 12/16頁
文件大?。?/td> 223K
代理商: LC8905V
Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD)
1. Data input and output addresses are allocated as follows:
2. The input command codes control the following settings:
System stop
Data input pin settings
Input bi-phase data output selection
Validity flag output selection
Audio data output format setting
DI1: Stops VCO operation and thus stops the system.
DI2: Selects which input data to demodulate.
DI3 and DI4: Select the E/DOUT pin output.
DI5 and DI6: Set the audio data output format.
All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used.
No. 5237-12/16
LC8905V
Data input or output
Figure 2: Microprocessor Interface Timing 1
Figure 3: Microprocessor Interface Timing 2
B0
B1
B2
B3
A0
A1
A2
A3
B0
B1
B2
B3
A0
A1
A2
A3
Data input
F7
1
1
1
0
1
1
1
1
EA
0
1
0
1
0
1
1
1
C bit output
F8
0
0
0
1
1
1
1
1
E9
1
0
0
1
0
1
1
1
Subcode Q, ID output
F9
1
0
0
1
1
1
1
1
E8
0
0
0
1
0
1
1
1
DI1
L
H
System
Operating
Stopped
DI2
L
H
Data demodulation input
DIN1
DIN2
DI3
L
H
DI4
L
H
L
H
E/DOUT
Emphasis
data output
Validity
flag output
DIN1 input
data output
DIN2 input
data output
DI5
L
H
DI6
L
H
L
H
16-bit right-
justified
MSB first
20-bit right-
justified
LSB first
20-bit right-
justified
MSB first
20-bit left-
justified
MSB first
DATAOUT
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