Figure 2-8. Per Quadrant Primary Clock Selection Figure 2-9. Per Quadrant Secondary Clock S" />
參數(shù)資料
型號： LFEC1E-5TN144C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 24/163頁
文件大小： 0K
描述： IC FPGA 1.5KLUTS 97I/O 144-TQFP
標(biāo)準包裝： 60
系列： EC
邏輯元件/單元數(shù)： 1500
RAM 位總計： 18432
輸入/輸出數(shù)： 97
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
2-9
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).
There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the
sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS
1. Smaller devices have fewer PLL related lines.
4 Secondary Clocks per Quadrant
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
Primary Clock
Secondary Clock
Routing
Clock to
each slice
GND
相關(guān)PDF資料
PDF描述
HCC65DRTF CONN EDGECARD 130PS DIP .100 SLD
FMC15DRYS CONN EDGECARD 30POS DIP .100 SLD
IR2166 IC PFC/BALLAST CONTROL 16-DIP
LFEC1E-3QN208I IC FPGA 1.5KLUTS 208PQFP
F920G106MAA CAP TANT 10UF 4V 20% 1206
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC1E-5TN144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3F256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3F484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*