參數(shù)資料
型號: LFECP10E-3QN208I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 119/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計: 282624
輸入/輸出數(shù): 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
3-23
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
fIN
Input Clock Frequency (CLKI, CLKFB)
25
420
MHz
fOUT
Output Clock Frequency (CLKOP, CLKOS)
25
420
MHz
fOUT2
K-Divider Output Frequency (CLKOK)
0.195
210
MHz
fVCO
PLL VCO Frequency
420
840
MHz
fPFD
Phase Detector Input Frequency
25
MHz
AC Characteristics
tDT
Output Clock Duty Cycle
Default Duty Cycle
Elected
3
45
50
55
%
tPH
4
Output Phase Accuracy
0.05
UI
tOPJIT
1
Output Clock Period Jitter
fOUT >= 100MHz
+/- 125
ps
fOUT < 100MHz
0.02
UIPP
tSK
Input Clock to Output Clock Skew
Divider ratio = integer
+/- 200
ps
tW
Output Clock Pulse Width
At 90% or 10%
3
1—
ns
tLOCK
2
PLL Lock-in Time
150
s
tPA
Programmable Delay Unit
100
250
450
ps
tIPJIT
Input Clock Period Jitter
+/- 200
ps
tFBKDLY
External Feedback Delay
10
ns
tHI
Input Clock High Time
90% to 90%
0.5
ns
tLO
Input Clock Low Time
10% to 10%
0.5
ns
tRST
RST Pulse Width
10
ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.G 0.30
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