Figure 2-8. Per Quadrant Primary Clock Selection Figure 2-9. Per Quadrant Secondary Clock S" />
參數(shù)資料
型號(hào)： LFECP33E-5FN672C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 24/163頁
文件大?。?/td> 0K
描述： IC FPGA 32.8KLUTS 672FPBGA
產(chǎn)品培訓(xùn)模塊： LatticeECP3 Introduction
標(biāo)準(zhǔn)包裝： 40
系列： ECP
邏輯元件/單元數(shù)： 32800
RAM 位總計(jì)： 434176
輸入/輸出數(shù)： 496
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-FPBGA（27x27）
2-9
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).
There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the
sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS
1. Smaller devices have fewer PLL related lines.
4 Secondary Clocks per Quadrant
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
Primary Clock
Secondary Clock
Routing
Clock to
each slice
GND
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